Reliability Of Electronic Systems Research Articles

Capacitance Evaluation of Metallized Polypropylene Film Capacitors Considering Cumulative Self-Healing Damage

Self-healing (SH) in metallized polypropylene film capacitors (MPPFCs) can lead to irreversible damage to electrode and dielectric structures, resulting in capacitance loss and significant stability degradation, especially under cumulative SH conditions. To enhance the reliability assessment of MPPFCs post-SH, this study conducted SH experiments on MPPFCs, examined the damage patterns of the electrodes and dielectric films, and proposed a novel capacitance evaluation method for MPPFCs under cumulative SH conditions. The results reveal that with increasing SH voltage, the number of dielectric layers experiencing single SH breakdowns rises, SH energy significantly escalates, and the loss area of the electrode due to high-temperature evaporation expands. Under cumulative SH conditions, the number of SH events is linearly correlated with the total number of SH-breakdown film layers and shows an exponential decay with the average single SH energy. By utilizing a Support Vector Machine (SVM) to classify the SH condition and damage features within the capacitor based on the correlation and distribution patterns of SH feature parameters, this study introduces an advanced method for evaluating the capacitance of MPPFCs under cumulative SH conditions. This method promises to improve the predictive maintenance and reliability of power electronic systems utilizing MPPFCs.

A 25 Mbps 15 ns Propagation Delay 150 kV/μs CMTI Configurable Dual-Channel Capacitive Digital Isolation Driver.

Electrical isolation devices are essential components for safeguarding the reliability of electronic systems under harsh conditions. Digital isolators are widely used in low-power circuits due to their high immunity to disturbances. In this paper, a capacitive digital isolator for high-efficiency power supply scenarios is proposed with a high common-mode transient immunity (CMTI) and high data transmission rate. The on-off keying (OOK) modulation technique is used to ensure a high speed and accurate signal transmission. A fully integrated high-voltage level-shift driver with an ns-scale delay is proposed for increasing the drive capacity. Post-simulation results in Cadence IC 6.1.7 with the standard 0.18 μm CMOS process show that the proposed architecture achieves a 25 Mbps data transmission rate and 15 ns typical propagation delay with output peak currents of 2 A/4 A, respectively. Meanwhile, a CMTI of more than 150 kV/μs is realized.

Ultrafast Self‐Powered Ti–Zn–N Photodetector‐Based Optocoupler for Power Electronics Applications

This study presents an early exploration into the application of a self‐powered photodetector based on titanium zinc nitride (TiZnN) films in power electronics, aiming to overcome inherent limitations of conventional optocouplers such as low switching speed and specific operating voltage requirements. The fabricated device demonstrates excellent performance metrics, including photosensitivity of 136, the responsivity of 3.22 mA W−1 at −8 V bias, and a peak detectivity of 1.76 × 108 Jones at 0 V bias. Remarkably, ultrafast rise (τs) and decay times (τd) of 0.11 and 0.10 ms, respectively, are achieved, alongside broad‐band spectral absorption characteristics. Experimental validation showcases the efficacy of the TiZnN‐based optocoupler in practical applications, notably in power electronics triggerable relay systems and AC–AC converters. Leveraging the self‐powering capability inherent to the TiZnN photodetector, this optocoupler eliminates external power source dependencies, thereby enhancing its versatility and applicability in diverse electronic systems. The rapid response time of the device and broad spectral absorption further underscore its suitability for high‐speed signal transmission across varied operating conditions. This research paves a path for developing stable, cost‐effective, and self‐powered ultrafast optocouplers, eliminating concerns about compromising electrical signal transit. These advancements hold significant implications for enhancing electronic system performance, reliability, and functionality in critical applications.

Smart Circuit Design Machine Learning-Driven Optimization for Enhanced Performance in Electronics and Computer Engineering.

In the realm of Electronics and Computer engineering, achieving optimal performance of circuits amidst escalating complexity poses significant challenges. Traditional manual optimization techniques are often inadequate to navigate the intricacies of modern electronic systems. This paper advocates for the adoption of machine learning-driven optimization as a transformative approach to smart circuit design. By leveraging machine learning algorithms, engineers can systematically explore the expansive design space, discern complex relationships between circuit parameters and performance metrics, and ultimately enhance the efficiency and effectiveness of electronic circuits. This paper comprehensively reviews the application of machine learning techniques in circuit design optimization. Supervised learning algorithms such as neural networks, support vector machines, and decision trees enable the modeling of intricate interdependencies within electronic circuits. Unsupervised learning techniques, including clustering and dimensionality reduction, facilitate efficient exploration of the design landscape by identifying patterns and correlations. Additionally, reinforcement learning algorithms offer an autonomous approach to circuit optimization through iterative learning and refinement. Real-world applications of machine learning-driven optimization in electronics and computer engineering span various domains, including power-efficient integrated circuits, signal processing algorithm optimization, and layout optimization for enhanced performance and reliability. Moreover, machine learning techniques play a crucial role in mitigating variability in semiconductor manufacturing processes, ensuring robustness and reliability of electronic systems in the face of uncertainties. Despite the promising potential of machine learning in circuit design optimization, challenges such as dataset acquisition, model interpretability, and scalability to complex circuits persist. Addressing these challenges requires innovative research endeavors, including the development of hybrid optimization techniques and novel hardware architectures. DOI: https://doi.org/10.52783/tjjpt.v45.i02.6339

WAYS TO REDUCE THE IMPACT OF PULSATIONS IN LOCAL POWER SUPPLY ROBOTIC SYSTEMS

An analysis of the changes in the flow of pulsation transforming the energy-dynamic indicators of on-board power electronics systems has shown that there are several options for solving this problem.
 The article outlines the main options for the current problem of pulsation in the energy systems of autonomous electrical systems, such as UAVs, robotic complexes, and other systems. The effectiveness of changes in pulsation is examined, in addition to directly assessing the effectiveness of stagnation strategies and methods. Also in the statistics, the optimal technical solutions for specific operating minds were identified.
 The prospects and future directives have been predicted based on the proposals for further research in the sphere of changes in pulsation in local life systems.
 In the future, it is predicted and supported by the development of technology and innovation in this country.
 To sum up, we can say that the statistics have analyzed the changes in pulsation in robotic local power supply systems, which is one of the key directions in the field of electrical engineering and electronics. Increased attention to this problem is due to the need for assured stability, reliability and greater energy efficiency of electronic systems. Research in this area is aimed at developing more comprehensive methods and strategies for reducing noise and pulsation in electrical systems.
 Assessing the effectiveness of stagnant methods, promoting the development of new technologies and innovation, as well as developing promising directions in this field opens the way to creating more stable and adaptive living systems. Replacement of advanced electronic filters, voltage stabilizers, selection of new materials and components, integration of intelligent energy management systems and optimization of essential energy resources local power supply systems – the whole purpose is to directly conduct further investigations.
 The growing demand for stable and efficient electronic systems is driven by current research and the introduction of new technologies to change pulsation. Technological developments and scientific research in this area open up broad prospects for reducing the power supply and ensuring the stability of the functioning of modern electronic devices.

Design and Implementation of SRAM Using Verilog

Abstract: This comprehensive review delves into the intricate realm of the Static Random-Access Memory (SRAM) design and implementation, elucidating its pivotal role in shaping the performance, efficiency, and reliability of contemporary electronic systems, involving applications in ASIC devices. With a primary focus on the integration of Verilog, a hardware description language (HDL), the paper provides an in-depth background on SRAM, meticulously detailing its architecture, operation, and overall significance in electronic systems. The review meticulously addresses challenges inherent in SRAM design, encompassing considerations such as power consumption, speed, and area efficiency. Significantly, it underscores the crucial role of Verilog by delving into its syntax, modules, and procedural constructs, showcasing its application in modeling key SRAM components. The discussion extends to design trade-offs, including size, speed, and power consumption, illustrating how Verilog plays a pivotal role in facilitating optimal parameter optimization. The review seamlessly integrates technical concepts like RTL (Register Transfer Level), and procedural assignments, ensuring a comprehensive exploration of SRAM design intricacies. Additionally, it introduces terms such as testbench, bitcell and power reduction, further enhancing the reader's understanding of the complex interplay between Verilog and SRAM design.

Analysis of the Interference Effects in CMOS Image Sensors Caused by Strong Electromagnetic Pulses

With the electromagnetic environment becoming increasingly complex, it is crucial to address the risk posed by electromagnetic pulse, which critically impairs the performance and reliability of electronic systems based on complementary metal oxide semiconductor (CMOS) image sensors. In this context, research on the failure types of CMOS image sensors in a high-power electromagnetic environment, caused by strong electromagnetic pulses and the rapid evaluation method of interference immunity, has garnered significant interest. This paper conducts electromagnetic pulse simulation experiments on CMOS image sensors to first study their failure types, such as image abnormalities and functional interruption, and then identify the corresponding failure criteria. Furthermore, this study builds on the small sample test evaluation method to investigate the interference threshold of functional interruptions in CMOS image sensors by calculating the failure probability at different field strengths. The obtained data were combined with the Weibull distribution function for fitting, the results of which found the interference threshold to be at 40.4 kV/m. The findings of this study provide a basis for evaluating the survivability of CMOS image sensors and their associated reinforcement technology in high-power electromagnetic environments.

Cosmic Radiation Reliability Analysis for Aircraft Power Electronics

Cosmic Ray induced failures are a major concern for the electronic system reliability of airborne and space systems. Power system voltages on aerospace platforms are on a steady upward trend. High voltage power converters suffer from Single Event Burnout failures caused by cosmic rays. The established standards propose a scaling factor based on measured background galactic cosmic rays intensity at operating altitude to apply de-rating factors. The radiation environment in the atmosphere can be increased due to the cascading of primary solar energetic particles during solar eruptions. In this work, the altitude profile of the radiation environment is simulated using a GEANT4 Monte-Carlo code. The failure rates due to both background Galactic Cosmic Rays and Solar Energetic Particles are quantitatively evaluated. Further to the known influence of geomagnetic shielding of cosmic rays, the geographical distribution of cosmic rays at flight altitudes of 10 km are also presented. The estimated cosmic ray intensity can then be combined with experimentally measured failure rate data to predict the impact on the reliability of power converters, giving a new level of accuracy in the modeling of such failure mode in more electric aircraft applications. It is shown for the first time in the scientific literature by using experimental data and state-of-the-art models, that the solar energetic particles storms fluxes vastly exceed the recommended standard and constitute a risk for the power electronics reliability.

Development and Fabrication of MOSFET-Based Radiation Dosimeter (RadFET) for Enhanced Performance in Space Missions

This work presents the development and fabrication process of a radiation dosimeter based on Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) technology, known as RadFET. The aim of this study is to determine the specifications of the RadFET sensor for use in space missions by the Egyptian Space Agency in SPNeX mission. We have successfully determined the sensor specifications, specified the required electronic components for readout circuits, and confirmed the correct operation of the RadFET device through device simulations and radiation-induced damage models. The fabrication process was conducted at Zewail City of Science, Technology and Innovation cleanroom facility, utilizing Sentaurus TCAD for device and process simulations. We have conducted fabrication experiments for phosphorus spin-on dopant application, dry oxide growth, and wet oxidation using water vapor bubblers. The dosimeter readout PCB fabrication and assembly phases have been successfully completed. The developed RadFET dosimeter holds great promise for radiation monitoring in space missions, ensuring enhanced safety and reliability of electronic systems.

Temperature Hotspot Detection on Printed Circuit Boards (PCBs) Using Ultrasonic Guided Waves-A Machine Learning Approach.

This paper addresses the challenging issue of achieving high spatial resolution in temperature monitoring of printed circuit boards (PCBs) without compromising the operation of electronic components. Traditional methods involving numerous dedicated sensors such as thermocouples are often intrusive and can impact electronic functionality. To overcome this, this study explores the application of ultrasonic guided waves, specifically utilising a limited number of cost-effective and unobtrusive Piezoelectric Wafer Active Sensors (PWAS). Employing COMSOL multiphysics, wave propagation is simulated through a simplified PCB while systematically varying the temperature of both components and the board itself. Machine learning algorithms are used to identify hotspots at component positions using a minimal number of sensors. An accuracy of 97.6% is achieved with four sensors, decreasing to 88.1% when utilizing a single sensor in a pulse-echo configuration. The proposed methodology not only provides sufficient spatial resolution to identify hotspots but also offers a non-invasive and efficient solution. Such advancements are important for the future electrification of the aerospace and automotive industries in particular, as they contribute to condition-monitoring technologies that are essential for ensuring the reliability and safety of electronic systems.

Advancements in Electric Vehicle PCB Inspection: Application of Multi-Scale CBAM, Partial Convolution, and NWD Loss in YOLOv5

In the rapidly evolving electric vehicle industry, the reliability of electronic systems is critical to ensuring vehicle safety and performance. Printed circuit boards (PCBs), serving as a cornerstone in these systems, necessitate efficient and accurate surface defect detection. Traditional PCB surface defect detection methods, like basic image processing and manual inspection, are inefficient and error-prone, especially for complex, minute, or irregular defects. Addressing this issue, this study introduces a technology based on the YOLOv5 network structure. By integrating the Convolutional Block Attention Module (CBAM), the model’s capability in recognizing intricate and small defects is enhanced. Further, partial convolution (PConv) replaces traditional convolution for more effective spatial feature extraction and reduced redundant computation. In the network’s final stage, multi-scale defect detection is implemented. Additionally, the normalized Wasserstein distance (NWD) loss function is introduced, considering relationships between different categories, thereby effectively solving class imbalance and multi-scale defect detection issues. Training and validation on a public PCB dataset showed the model’s superior detection accuracy and reduced false detection rate compared to traditional methods. Real-time monitoring results confirm the model’s ability to accurately detect various types and sizes of PCB surface defects, satisfying the real-time detection needs of electric vehicle production lines and providing crucial technical support for electric vehicle reliability.

Intermittent fault diagnosis of analog circuit based on enhanced one-dimensional vision transformer and transfer learning strategy

As the major cause of false alarms in built-in test (BIT) system, intermittent faults of analog circuits may trigger abnormal equipment shutdown and lead to catastrophic accidents. With complete randomness and great non-repeatability, intermittent faults are arduous to be detected. To enhance the reliability and safety of electronic systems, an end-to-end approach based on enhanced one-dimensional Vision Transformer (1DViT) is proposed to realize intelligent diagnosis for intermittent faults of analog circuits. The signal anomaly caused by intermittent faults can be regarded as a kind of random anomaly from global perspective, and there are also rich local feature information in the fault interval. Completely composed of self-attention mechanism, Vision Transformer possesses prominent performance on extracting global features and modelling global representations, thus can be applied to identify intermittent faults. Meanwhile, to further enrich the feature representation, one multi-scale convolution fusion module (MSC) incorporating a series of convolution operations is designed and combined with 1DViT to extract and fuse the valuable local information. However, in practical test, due to the complex operation process, it is cumbersome to collect sufficient fault data to guarantee the effective training of the proposed model. To cope with this problem, transfer learning strategy is introduced. The model will be first pre-trained with adequate simulation data which is easily accessible, and then fine-tuned with a relatively small amount of actual fault data to help match the practical feature distribution. Experiments on two typical circuits demonstrate that the proposed method could achieve excellent diagnostic result in practical test.

Intermittent fault diagnosis for electronics-rich analog circuit systems based on multi-scale enhanced convolution transformer network with novel token fusion strategy

Intermittent faults of analog circuits in the core area of electronic systems may induce false alarms of built-in test (BIT) system and even cause catastrophic accidents. Due to notable non-repeatability and high randomness, intermittent faults are arduous to be detected. In order to enhance the safety and reliability of electronic systems, an end-to-end diagnostic framework based on multi-scale enhanced convolution Transformer network (MSECTN) with novel token mixing and fusion strategy has been developed. Intermittent fault is a kind of random fault from global perspective, and there is also abundant local information inherent in the fault interval. Wholly composed of self-attention mechanisms, Transformer network possesses prominent capability of representing global features and modelling distant temporal associations, thus can be applied to identify intermittent faults. Meanwhile, introduce the local perception of convolution operation into Transformer network. One convolution embedding and convolutional multi-head self-attention module are designed to capture more abundant local details. Since the information at single scale cannot sufficiently reflect the circuit status, multi-scale convolution embedding with kernels in different sizes is performed to enrich the feature representation. Moreover, one token mixing strategy incorporating Fourier transformation, pooling operation, and depth-wise convolution is proposed to simultaneously model the frequency correlation and enhance the information interaction among spatially adjacent tokens. In order to excavate more inherent and distinguishing features, a novel token fusion strategy is designed to eliminate the effects of redundant feature information. Experimental results on two typical analog circuits demonstrated that the proposed approach can effectively identify different intermittent faults.

Investigation and Comparison of Temperature-Sensitive Electrical Parameters of SiC mosfet at Extremely High Temperatures

Due to the excellent silicon carbide (SiC) material characteristics, SiC MOSFETs can operate at extremely high temperatures and can be used in harsh environment applications. In this case, it is crucial to ensure the reliability of the power electronic systems. The temperature-sensitive electrical parameters (TSEPs) have been used for online junction temperature monitoring to monitor the health condition of the SiC MOSFET at low temperatures (<175℃). However, the performance of the TSEPs at extremely high temperatures is still unknown, and the influence of temperature on the TSEPs of SiC MOSFET at extremely high temperatures is unclear. In this article, the theoretical mechanisms of the impact of the extremely high temperature on TSEPs are investigated in detail. In particular, the different effects of high temperature on the turn-on delay time and turn-off delay time are discussed carefully. Based on the high-temperature characteristic test method proposed, the TSEPs of SiC MOSFET (including static and dynamic characteristics) are tested and analyzed comprehensively from room temperature to 375℃. And the sensitivity and linearity of the TSEPs in different temperature ranges are analyzed and compared. According to the results, threshold voltage and turn-off delay time are the two TSEPs with good sensitivity and linearity over a wide temperature range (from room temperature to 375℃). And the linearity of turn-off delay time is the best among all TSEPs over a wide temperature range.

RUL prediction for AECs of power electronic systems based on machine learning and error compensation

Aluminum electrolytic capacitor (AEC) is one of the most pivotal components that affect the reliability of power electronic systems. The electrolyte evaporation and dielectric degradation are the two main reasons for the parametric degradation of AEC. Remaining useful life (RUL) prediction for AEC is beneficial for obtaining the health state in advance and making reasonable maintenance strategies before the system suffers shutdown malfunction, which can increase the reliability and safety. In this paper, a hybrid machine learning (ML) model with GRU and PSO-SVR is proposed to realize the RUL prediction of AEC. The GRU is used for the recursive multi-step prediction of AEC to model the times series of AEC, SVR optimized by PSO for hyper-parameters is applied for error compensation caused by recursive GRU. Finally, the proposed model is validated by two kinds of data sets with accelerated degradation experiments. Compared with the other methods, the results show that the proposed scheme can obtain greater prediction performance index of RUL under different prediction time points, which can support the technology of health management for power electronic system.

Neutron Irradiation Testing and Monte Carlo Simulation of a Xilinx Zynq-7000 System on Chip

The reliability of nanoscale electronic systems is important in various applications. However, they are becoming increasingly vulnerable to atmospheric neutrons. This research conducted spallation neutron irradiations on a Xilinx Zynq-7000 system on a chip using the China Spallation Neutron Source. The results were analyzed in combination with a Monte Carlo simulation to explore the impact of atmospheric neutrons on the single event effects of the target system on chip. Meanwhile, the contribution of thermal neutrons to the chip’s single event effect susceptibility was also assessed. It was found that absorbing thermal neutrons with a 2 mm Cd sheet can protect against the single event effect on the system on the chip by about 44.4%. The effects of B and Hf elements, inside the device, on a single event effect of the Xilinx Zynq-7000 system on chip were evaluated too. Additionally, it was discovered that 10B interacting with thermal neutrons was the primary cause of the thermal neutron-induced single event effect in the system on chip. Although Hf has a high neutron capture cross section, its presence does not significantly affect the sensitivity to single event effects. However, during atmospheric neutron irradiation, the presence of Hf increases the possibility of depositing the total dose in the tested chip.

Characterising Solder Materials from Random Vibration Response of Their Interconnects in BGA Packaging

Solder interconnection in electronic packaging is the weakest link, thus driving the reliability of electronic modules and systems. Improving interconnection integrity in safety-critical applications is vital in enhancing application reliability. This investigation qualifies the random vibration response of five essential solder compositions in ball grid array (BGA) solder joints used in safety-critical applications. The solder compositions are eutectic Sn63Pb37 and SnAgCu (SAC) 305, 387, 396, and 405. Computer-aided engineering (CAE) employing ANSYS finite element analysis and SolidWorks software is implemented in this investigation. The solder Sn63Pb37 deformed least at 0.43 µm, followed by SAC396 at 0.58 µm, while SAC405 deformed highest at 0.88 µm. Further analysis demonstrates that the possession of a higher elastic modulus and mass density culminates in lower solder joint deformation. Stress is concentrated at the periphery of the solder joints in contact with a printed circuit board (PCB). The SAC396 solder accumulates the lowest stress of 14.1 MPa, followed by SAC405 at 17.9 MPa, while eutectic Sn63Pb37 accrues the highest at 34.6 MPa. Similarly, strain concentration is found at the interface between the solder joint and copper pad on a PCB. SAC405 acquires the lowest elastic strain magnitude of 0.0011 mm/mm, while SAC305 records the highest strain of 0.002 mm/mm. These results demonstrate that SAC405 solder has maximum and SAC387 solder has minimum fatigue lives.

Real-Time Average Junction Temperature Estimation for Multichip IGBT Modules With Low Computational Cost

The junction temperature of the insulated gate bipolar transistor (IGBT) modules is a vital parameter for the reliability of the power electronic system. For effective thermal management, it is necessary to estimate junction temperature in real time. However, existing thermal models have limitations to achieve fast temperature prediction for multichip IGBT modules. In this study, we investigate the real-time junction temperature prediction for multichip IGBT modules with low computational cost. According to the power module&#x0027; structure, an average 2D thermal model with physical significance is proposed to predict the virtual junction temperature for multichip IGBT modules, which can be extracted from finite element model based on the least square method. To further improve the computational efficiency, a temperature predictor based on the staggered cycle-by-cycle calculation method is proposed and its prediction error under various extreme operation conditions is analyzed by enumeration method. Finally, the comprehensive experimental results verify the effectiveness of the proposed average thermal model and junction temperature prediction method.

Adaptive DC Voltage Control for Optimal Junction Temperature Redistribution Under Stall Condition of Electric Machine Drive Inverter

Active thermal controls (ATCs) are becoming an efficient solution to enhance the reliability of power electronics components and systems. In the applications of electric machine drive, ATCs under abnormal conditions, such as overstress in a relatively short timescale, still need further investigations. As one of the control freedoms, the dc voltage has a strong impact to the loss and thermal behaviors of power semiconductor devices. In this letter, the loss and thermal characteristics under the stall condition of the electric machine drive converter are investigated, and an ATC method with Adaptive dc voltage control (ADVC) is proposed. By using the proposed ADVC, the conduction loss and switching loss of the power devices are redistributed intentionally, so that the total power loss and junction temperature under the stall condition can be minimized. Furthermore, a speed-based-coefficient digital filtering algorithm is applied for dc voltage reference calculation, so that the ADVC performs self-adaptive to the rotor speed and be integrated into the original control structure of the drive converter. Simulations and experimental results are provided to validate the effectiveness of the proposed method.

균열에 대한 전기적 모델과 S-파라미터 패턴을 이용한 솔더조인트 신뢰성 분석

Purpose: Electrical interconnects affect the reliability and performance of entire electronic systems - especially as operating frequencies and clock speeds in processors are increasing annually. We suggest the S-parameter pattern analysis method is used to evaluate the reliability of the commonly-used solder-joint interconnect.BRMethod: An impedance model of the solder-joint interconnect was developed to study the effect of crack evolution. Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, using a suggested impedance model, were then performed and the crack evolution was tracked using the S-parameter pattern analysis.BRResults: In the crack initiation phase, a resonance peak occurred on the S-parameter pattern and it the peak moved toward lower frequencies as the crack propagated until failure.BRConclusion: This study demonstrated that monitoring the resonant frequency in the S-parameter pattern can predict the initiation and evolution of cracks in the solder-joint interconnects.