Abstract
Purpose: Electrical interconnects affect the reliability and performance of entire electronic systems - especially as operating frequencies and clock speeds in processors are increasing annually. We suggest the S-parameter pattern analysis method is used to evaluate the reliability of the commonly-used solder-joint interconnect.BRMethod: An impedance model of the solder-joint interconnect was developed to study the effect of crack evolution. Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, using a suggested impedance model, were then performed and the crack evolution was tracked using the S-parameter pattern analysis.BRResults: In the crack initiation phase, a resonance peak occurred on the S-parameter pattern and it the peak moved toward lower frequencies as the crack propagated until failure.BRConclusion: This study demonstrated that monitoring the resonant frequency in the S-parameter pattern can predict the initiation and evolution of cracks in the solder-joint interconnects.
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