Chip Reliability Research Articles

Verifying chip designs at RTL level

As chip designs become increasingly complex, the potential for errors and defects in circuits inevitably rises, posing significant challenges to chip security and reliability. This study investigates the use of the SAT-based bounded model checking (BMC) for Propositional Projection Temporal Logic (PPTL) to verify Verilog chip designs at the register transfer level (RTL). To this end, we propose an algorithm to implement automated extraction of state transfer relations from AIGER netlist and construction of Kripke structure. Additionally, we employ PPTL with the full regular expressiveness to describe the circuit properties to be verified, especially the periodic repetitive properties. This is not possible with Linear Temporal Logic (LTL) and Computational Tree Logic (CTL). By combining the PPTL properties with finite system paths and transforming them into conjunctive normal forms (CNFs), we utilize an SAT solver for verification. Experimental results demonstrate that our verification tool, SAT-BMC4PPTL, achieves higher verification efficiency and comprehensiveness.

Design of radiation hardened latch with low delay and tolerance of quadruple-node-upset in 32 nm process

As integrated circuit technology continues to shrink, single-event multiple-node-upset induced by charge sharing effect has become an important factor affecting chip reliability. This paper proposes two quadruple-node-upset hardened latches: 4DICE-C and 4DICE-V. These two latches are both based on dual-interlocked-storage-cell (DICE) that can achieve single-node-upset self-recovery. Besides, a quadruple-modular redundancy fault-tolerant mechanism is constructed. The 4DICE-C uses the clocked quadruple-input C-element at the output stage, the 4DICE-V uses clocked voter at the output stage. Compared with previous hardened latches containing C-elements, the 4DICE-V is less sensitive to high impedance state and can efficiently tolerate soft errors at internal nodes. In addition, compared with previous single-event triple-node-upset and quadruple-node-upset hardened latches, the 4DICE-C latch has achieved 100 % tolerance efficiency of single-event quadruple-node-upset, the best delay overhead and APDP comprehensive overhead, 18.69 % lower than average delay.

Reproducible, Accurate, and Sensitive Food Toxin On-Site Detection with Carbon Nanotube Transistor Biosensors.

Field-effect transistor (FET) biosensors based on nanomaterials are promising in the areas of food safety and early disease diagnosis due to their ultrahigh sensitivity and rapid response. However, most academically developed FET biosensors lack real-world reproducibility and comprehensive methodological validation to meet the standards of regulatory bodies. Here, highly uniform and well-packaged semiconducting carbon nanotube (CNT) FET biosensor chips were developed and assessed for the plug-and-play sensing for the rapid and highly sensitive detection of aflatoxin B1 (AFB1) in real food samples to meet international standards. In order to meet the requirements for reproducibility and stability, a scalable residual-free passivation and packaging process was developed for CNT FET biosensors. Portable detection systems were then constructed for on-site detection. The resulting packaged chips were functionalized with nucleic aptamers to enable highly selective detection of AFB1 in food samples with a detection limit (LOD) of 0.55 fg/mL (standard) for AFB1 and cross-reactivity coefficients to interferences as low as 1.8 × 10-7 in simulated solutions. Utilizing the portable detection system, on-site real food detection was achieved with a rapid response time less than 60 s, and LOD of 0.25 pg/kg (standard) in complex corn sample matrices. Single-blind tests demonstrated the ability of the chips to detect AFB1-positive food with 100% accuracy, using a set of 30 peanut samples. Validation experiments confirmed that the detection range, stability, and repeatability met international standards. This study showcased the accuracy, reliability, and potential practical applications of CNT FET biosensor chips in areas such as food safety and rapid biomedical testing.

Texture Evolution of High-purity Tantalum during 90°Clock Rolling

Abstract When fabricating high-purity tantalum targets for the sputtering procedure of integrated circuit manufacturing, a through-thickness texture gradient can form in the rolled tantalum (Ta) plate. This texture gradient hinders the target sputtering performance, reducing chip reliability. This study investigated the texture evolution during the 90°clock rolling through experimental and simulation methods. Balancing the plane strain deformation with the surface shear strain deformation during fabrication and limiting the total rolling reduction to no more than 85% can weaken the through-thickness texture gradient in the Ta plate. A crystal plasticity finite element method (CPFEM) model was developed to simulate the 90°clock rolling procedure in the ABAQUS/Explicit software. The simulation and the experimental results are in agreement, with slight differences in texture type and intensity due to tantalum’s complex slip behaviors.

Improving thermal stability and reliability of power chips by sintering foam structure layer

In order to ensure the high-temperature reliability of device in high temperature service, a new sintered structure layer, nano-Ag paste filling graphene reinforced Ni foam, was designed to realize the chip packaging in this work. This layer had excellent reliability and high-temperature heat dissipation stability, which benefit from the higher proportion of low-angle grain boundaries, finer grains and excellent heat dissipation capacity of graphene. The foam structure had favorable stress release effect, which made the sintered layer had high service reliability. The excellent heat dissipation ability of graphene overcomes the inherent defect of slow heat dissipation of the device under high temperature environment.

Effect of the pulsed current of on-chip thermoelectric cooler on temperature response during thermal shock in localized cooling

On-chip thermoelectric cooling (TEC) emerges as a promising solution to address the issue of localized chip overheating, effectively mitigating thermal shock induced by local heat flow conduction and enhancing both reliability and performance of chips. In this study, a three-dimensional numerical model is developed to investigate the effectiveness of on-chip thermoelectric cooler’s pulse current in mitigating temperature fluctuations caused by thermal shock at hot spots. The influence of the magnitude and lag time of the pulse current on the temperature fluctuation of Si chip during thermal shock is analyzed. The calculation results show that the implementation of on-chip TEC can effectively mitigate the issue of localized temperature overheating caused by thermal shock. By adjusting the maximum and minimum current of the on-chip thermoelectric cooler, it is possible to mitigate the fluctuation amplitude of chip temperature induced by thermal shock at the hot spot. The findings also indicate that the lag time between input current and thermal shock can lead to an increase in the maximum temperature of the chip. In addition, experimental results using commercially thermoelectric cooler also show that when the input current of TEC is pulse current, the temperature fluctuation caused by thermal shock can be reduced better.

Aggravated NBTI reliability due to hard-to-detect open defects

FinFET technology has become an attractive candidate for high-performance and power-efficient applications. In the other hand, the behavior of FinFET devices is influenced by self-heating effect (SHE) due to its 3D structure, low thermal coupling and quantum confinement effect, among others. SHE degrades the device’s performance and could worsen reliability mechanisms like NBTI. In addition, some hard-to-detect open defects in FinFET based-circuits using logic gates designed with multi-fin and multi-finger techniques may escape the test and present abnormal static currents, which may increase the impact of self-heating effect and make the NBTI degradation more severe. Hence, it is crucial to accurately determine the temperature profiles of those chips passing the test and presenting abnormal static currents. This paper investigates the reliability of chips passing the test with abnormal static currents using Sentaurus Technology Computer-Aided Design (TCAD). FinFET transistors are calibrated with Intel 14-nm FinFET technology. Our TCAD simulation framework determines accurately the temperature and NBTI degradation. Using the TCAD information, the device degradation over time can be predicted. Moreover, the delay penalization of a critical logic path of an ISCAS benchmark circuit is investigated. The delay penalization of logic paths, attributed to the defect and NBTI, is analyzed with varying logic depths, emphasizing the importance of addressing critical paths with different logic depths. Our study leads to new considerations for improving the prediction of circuit reliability and taking countermeasures.

Investigation on the thermal characteristics of electronic system and prediction of chip temperature by machine learning

In this work, the thermal characteristics and steady-state temperatures (SST) of CPU and FPGA of electronic system in nuclear power plant are explored. Finite element analysis is performed to simulate the test process. Furthermore, three machine learning algorithms are used to predict chips temperatures at different operating conditions. It is found that when the ambient temperature is 20 °C and all the fans are power-off, the SST of the CPU and FPGA reaches 75 °C and 72 °C, respectively. While when the fans are power-on, the SST of the CPU and FPGA drops to 37.5 °C and 33 °C. When the ambient temperature increases to 55 °C and all the fans are power-on, the SST of the CPU and FPGA is 72.3 °C and 68.2 °C, respectively. The finite element model is verified and used to generate test data. Three machine learning models are verified by predicting the SST of CPU and FPGA under different operating conditions. It is found that M-SVR has better prediction ability than DT and ANN. The findings can be used for chip reliability evaluation of other electronic system devices, and provide a new method for predicting the possible steady-state temperature of chips under different service conditions.

Review on low power design of digital integrated circuits

Abstract With the rapid development of science and technology, integrated circuit (IC) plays an increasingly important role in our daily life. Moreover, due to the increasing reduction of chip process size, the IC had greatly improved on its integration and performance. However, because of the improvement of the system complexity and the widely applied to various mobile devices, power consumption becomes an important limitation of the development in chip design. Power consumption not only affects the chip package type and cost, but also causes the increasing of chip temperature, which will directly affect the reliability of chips. On the other hand, high power consumption will also harm the stability of chips. Low power design are becoming more and more imminent, so low-power design are becoming a tendency of designing digital integrated circuits. This paper firstly introduces the importance of nowadays IC research, some background principles and research process of integrated circuits, then analyses the current challenges of designing low-power ICs and also research the power consumption of digital integrated circuits, later explores and analyses the low-power design methods in two different ways. And finally summarize the research status on low-power design circuits with some relevant personal views and the vision to the future are also put forward.

Enhancing chip performance and reliability by CMOS+X technologies

Enhancing chip performance and reliability by CMOS+X technologies

Research on Electromagnetic Environment Characteristic Acquisition System for Industrial Chips

With the system interconnection and intelligence of application scenario equipment, the electromagnetic environment of chips is becoming more and more complex. Problems such as communication interruption and data loss caused by electromagnetic interference often occur. The electromagnetic reliability of chips has become an important index to measure their availability. In order to effectively detect the electromagnetic reliability of industrial chips applied to specific scenarios, it is necessary to measure and analyze the electromagnetic characteristics of the application scenarios, as the boundary conditions of the electromagnetic protection simulation analysis and design of the chip, and to develop Electromagnetic Compatibility (EMC) test items, test limits and test methods suitable for carrying out tests and monitoring on chips. The paper presents an acquisition system, which can complete the collection of transient electromagnetic interference, steady electromagnetic field, temperature, humidity and near-field data. The transient interference measurement frequency range is 300 kHz–500 MHz, with a rising edge of 1.5 ns; the steady-state electromagnetic field measurement frequency ranges from 100 Hz to 3 GHz. By collecting the electromagnetic environmental characteristics of chips and analyzing situations in which chips are prone to interference, protective measures can be implemented.

Efficient topology reconfiguration for NoC-based multiprocessors: A greedy-memetic algorithm

In multi-core processor systems, the Network-on-Chip (NoC) serves as a vital communication infrastructure. To ensure chip reliability during potential failures, this paper proposes a two-level topology reconfiguration algorithm with core-level redundancy technology. Initially, a heuristic topology reconfiguration method utilizing a greedy strategy is proposed to perform local replacement of faulty processing elements (PEs) and generate an initial logical topology with shorter interconnection paths between PEs. Then, an intelligent optimization method based on memetic algorithm is introduced to optimize the generated initial topology for better communication performance. The experimental results demonstrate that compared to the current state-of-the-art algorithm, the proposed algorithm achieves an average improvement of 13.92% and 30.83% on various size topologies in terms of distance factor (DF) and congestion factor (CF), which represent communication delay and traffic balance respectively. The proposed algorithm significantly enhances the communication performance of the target topology, mitigating communication latency and potential congestion problems.

Low Stress TSV Arrays for High-Density Interconnection

In three-dimensional (3D) stacking, the thermal stress of through-silicon via (TSV) has a significant influence on chip performance and reliability, and this problem is exacerbated in high-density TSV arrays. In this study, a novel hollow tungsten TSV (W–TSV) is presented and developed. The hollow structure provides space for the release of thermal stress. Simulation results showed that the hollow W–TSV structure can release 60.3% of thermal stress within the top 2 μm from the surface, and thermal stress can be decreased to less than 20 MPa in the radial area of 3 μm. The ultra-high-density (1600 TSV∙mm−2) TSV array with a size of 640 × 512, a pitch of 25 μm, and an aspect ratio of 20.3 was fabricated, and the test results demonstrated that the proposed TSV has excellent electrical and reliability performances. The average resistance of the TSV was 1.21 Ω. The leakage current was 643 pA and the breakdown voltage was greater than 100 V. The resistance change is less than 2% after 100 temperature cycles from −40 to 125 °C. Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W–TSV was 31.02 MPa, which means that there was no keep-out zone (KOZ) caused by the TSV array. These results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.

A modified Qian-Liu constitutive model based on advanced packaging underfill materials

—The high integration and multifunctionality of microsystem packaging have led to a gradual reduction in packaging size, bringing changes in materials, structures, and processes. This has resulted in numerous issues related to structural reliability and signal integrity. To address the problems of stress concentration during chip packaging, underfill materials are typically introduced beneath the chip. Therefore, the appropriate underfill selection significantly impacts chip reliability. In this work, a modified Qian-Liu constitutive model is proposed to describe the viscoplastic deformation of underfill. The new model accurately predicted the overall trend of stress-strain behavior for the temperature range from 298K to 398K and the strain rate range from 0.0001s−1 to 0.00ls-1. Constitutive parameters of the underfill over a wide temperature range based on the modified Qian-Liu model were obtained. A comparison between the experiment and simulation verified that the modified Qian-Liu model reasonably simulated the viscoplastic stress-strain relationships for underfill materials.

Ultrathin Parylene C-based sensitivity-gain nanoplasmonic sensor integrated on VCSEL for Aβ42 detection

As Alzheimer's disease prevalence continues to rise, there is an increasing demand for efficient on-chip biosensors capable of early biomarker detection. This study presents a novel biosensor chip leveraging vertical cavity surface emitting laser (VCSEL) technology, with Parylene C serving as the antibody coupling layer and utilizing a streamlined one-step antibody modification method. Integration of Parylene C enhances chip sensitivity from 34.28 μW/RIU to 40.32 μW/RIU. Moreover, post-testing removal of Parylene C enables chip reusability without significant alteration of results. The sensor demonstrates effective detection of Aβ42, an Alzheimer's biomarker, exhibiting a linear range of 1–200 ng/mL and a detection limit of 0.26 ng/mL. These findings underscore the reusability and reliability of the ultrathin Parylene C-based VCSEL biosensor chip, highlighting its potential for point-of-care Alzheimer's disease diagnosis.

Thermal and supply voltage analysis of optimized ring oscillator for pixel detector readout chip

This paper provides a specific study of the upgrade of the ATLAS pixel detector in preparation for the upgrade of the Large Hadron Collider (LHC). The upgrade to High Luminosity-LHC (HL-LHC) is expected to start after the long shutdown in 2025-2027. The scheduled upgrade for ATLAS will be able to efficiently cope with the challenges caused by the high luminosity imposed by the HL-LHC. A new full-silicon Detector Inner Tracker (ITk) will replace the current ATLAS Inner Detector (ID). The ITk pixel detector will consist of more layers than in the current pixel detector. This study focuses on the Ring Oscillator (ROSC) sensors embedded in the ITkPix-V1 Front-End chip of the ATLAS ITk pixel detector. The paper reports the frequency response of the ROSC at various temperatures and voltage supply values. The results showed a high sensitivity of ROSCs frequencies to the applied voltage and the external temperatures which indicates the reliability of the ITkPix-V1 chip for the future ITk pixel modules.

Progress and comparison in nondestructive detection, imaging and recognition technology for defects of wafers, chips and solder joints

ABSTRACT As an essential part of integrated circuit, chip manufacturing has increasingly demanding requirements for quality, cost and others. Some technical limitations and the development direction of miniaturisation and high density have led to defects in the manufacturing process, which affect the performance and life of the chip. Therefore, the detection, identification and classification of defects are very important to improve the chip reliability. Based on the orderly and concise literature research, this paper focuses on a comprehensive review of the main research results in the field of non-contact non-destructive testing imaging methods for chip defects. Firstly, various defects that may occur in the chip design and packaging process are introduced. Then the contact detection methods including manual and probe method are clarified, and the principles, properties and development applications of NDT methods are introduced in detail, also the defect identification methods after imaging are briefly introduced. Moreover, the advantages and limitations of NDT technologies are summarised through comparative studies. Finally, the future development trend of non-destructive testing methods is predicted. This work hopes to provide some reference for the non-destructive testing of chips, which is of great significance for the health testing of chips in the electronics manufacturing industry.

Label-free microfluidic chip for segregation and recovery of circulating leukemia cells: clinical applications in acute myeloid leukemia.

We present a label-free microfluidic chip for the segregation of circulating leukemia cells (CLCs) from blood samples, with a focus on its clinical applications in Acute Myeloid Leukemia (AML). The microfluidic chip achieved an approximate capture efficiency of 92%. The study analyzed a comprehensive set of 66 blood specimens from AML patients in different disease stages, including newly diagnosed and relapsing cases, patients in complete remission, and those in partial remission. The results showed a significant difference in CLC counts between active disease stages and remission stages (p < 0.0001), with a proposed threshold of 5 CLCs to differentiate between the two. The microfluidic chip exhibited a sensitivity of 95.4% and specificity of 100% in predicting disease recurrence. Additionally, the captured CLCs were subjected to downstream molecular analysis using droplet digital PCR, allowing for the identification of genetic mutations associated with AML. Comparative analysis with bone marrow aspirate processing by FACS demonstrated the reliability and accuracy of the microfluidic chip in tracking disease burden, with highly agreement results obtained between the two methods. The non-invasive nature of the microfluidic chip and its ability to provide real-time insights into disease progression make it a promising tool for the proactive monitoring and personalized patient care of AML.

3D CT scan metrology for solder void formation analysis in ball grid array electronic chips

The miniaturization of silicon chips and the complexity of device functionality has driven the electronic packaging industry to find new methods to enhance the reliability of chips at a smaller size. Solutions such as Ball Grid Array (BGA) packages have contributed to the miniaturization of integrated circuits (ICs) and the reduction in their overall size. However, void formation in the solder joint is a weakness that can affect the robustness of the solder joint integrity, both mechanically and electrically. To detect these voids, metrology methods such as 3D Computed tomography (CT)-scan are used. 3D CT-scans can identify submicron-sized void defects in real-time during thermal tests, which can be utilized to help improve the quality control lines in the electronic chip manufacturing industries. In this paper, two types of BGA packages will be evaluated for solder joint properties. The prepared samples will be subject to high temperature stress conditions to assess the mechanism of void formation in solder joint. The prepared samples will be heated at 260 °C four times where the heating lasts 0, 5, 10, and 15 min, respectively. The prepared samples will be mounted on a PCB board and the results of the thermal stress tests will be analyzed using 3D X-ray CT scans. These 3D-CT scans used in tandem with a reconstruction and visualization software suite, will be utilized to observe changes such as void formation in the solder joint after each heating time. Unexpectedly, void size reduced between the first and second heat cycles on both samples but increased for the third and fourth heat cycles then.

Research on intermittent fault of bond wire under thermal and vibration shock based on simulation and experiments

As equipment usage environments become increasingly complex and harsh, the reliability of chips as the core of high-density integrated circuits becomes increasingly important. Bond wires, as weak links, are the focus of reliability research. Traditional research has focused on permanent failures, while intermittent failures have received little attention due to their unpredictable nature, but their existence cannot be ignored. This article simulates temperature shock and vibration environments on bond wires, demonstrating that the dangerous area of bond wires is located at the junction of the gold wire and the chip solder pad. It also explains that intermittent failures are caused by the degradation or potential damage of bond wires that are further damaged when subjected to environmental shocks, with the effective contact area of the damaged area changing with the shock and the resistance changing significantly. Based on the theory of contact resistance, relevant models were constructed for simulation, and the effect of micro-protrusion depth on contact resistance was studied. The article then designed and constructed an experimental circuit to carry out intermittent failure verification tests and studied the characteristics of intermittent failure currents. This research provides theoretical and technical support for the study of intermittent failures in high-density integrated circuits.