Reliability-aware Design Research Articles

Aging-Aware Critical Path Selection via Graph Attention Networks

In advanced technology nodes, aging effects like negative and positive bias temperature instability (NBTI and PBTI) become increasingly significant, making timing closure and optimization more challenging. Unfortunately, conventional critical path selection tools used in reliability-aware design flow cannot accurately identify critical paths under different aging conditions. To address this issue, we propose an aging-aware critical path selection flow comprising two parts: critical cell detection and path criticality computation. We employ graph-attention networks (GATs) to predict the critical cells in the aged circuits, and a path criticality computation algorithm that takes into account circuit-level and transistor-level parameters to generate path criticality rank lists. Our experimental results demonstrate that our GAT model outperforms classical machine learning models in detecting critical cells. Additionally, compared with the commercial tool, our aging-aware flow achieves an average accuracy of 99.52%, 98.69%, and 97.20% for top-10%, top-5%, and top-1% path sets respectively, in five industrial designs subjected to different aging conditions and workloads.

Reliability-aware design of Integrate-and-Fire silicon neurons

Variation in CMOS device parameters due to reliability issues like Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI), etc., has posed serious performance concerns in various digital and analog/mixed-signal circuit designs, which include neuromorphic circuits. CMOS-based neuromorphic circuits, also known as silicon neurons (SiNs), are designed to emulate the electrophysiological behavior of biological neurons. Neuromorphic systems are used to learn and adapt in various applications like image processing and classification, wearable/implantable systems, robotics, etc. that require high performance. It is therefore, important to analyze neuromorphic circuits performance over their lifetime. This is achieved by identifying the specific transistors affecting circuit performance and to come up with workable ways to solve these problems. In this work, we have investigated the combined effect of NBTI and HCI on two types of Integrate-and-Fire (I&F) SiNs, Axon-Hillock (AH) and Simplified Leaky Integrate-and-Fire (SLIF) circuits, using key performance parameters. Novel reliability-aware AH and SLIF circuits are proposed to mitigate the reliability issues. The proposed reliability-aware designs show negligible deviations in the performance parameters after degradation. The time-zero process variability analysis is also carried out for the proposed reliability-aware SiNs. The power consumption of existing and proposed reliability-aware neuron circuits is analyzed and compared.

A Survey of Real-Time Ethernet Modeling and Design Methodologies: From AVB to TSN

With the development of real-time critical systems, the ever-increasing communication data traffic puts forward high-bandwidth and low-delay requirements for communication networks. Therefore, various real-time Ethernet protocols have been proposed, but these protocols are not compatible with each other. The IEEE 802.1 Working Group developed standardized protocols named Audio Video Bridging (AVB) in 2005, and renamed it Time-Sensitive Networking (TSN) later. TSN not only adds new features but also retains the original functions of AVB. Proposing real-time Ethernet modeling and design methodologies is the key to meeting high-bandwidth and low-delay communication requirements. This article surveys the modeling from AVB to TSN, mainly including: (1) AVB and TSN modeling; (2) end-to-end delay modeling; (3) real-time scheduling modeling; (4) reliability modeling; and (5) security modeling. Based on these models, this article surveys the recent advances in real-time Ethernet design methodologies from AVB to TSN: (1) end-to-end delay analysis from AVB to TSN; (2) real-time scheduling from AVB to TSN; (3) reliability-aware design for TSN; and (4) security-aware design for TSN. Among the above four points, the last two points are only for TSN, because AVB lacks reliability and security mechanisms. This article further takes the automotive use case as an example to discuss the application of TSN in automobiles. Finally, this article discusses the future trends of TSN. By surveying the recent advances and future trends, we hope to provide references for researchers interested in real-time Ethernet modeling and design methodologies for AVB and TSN.

Guest Editor's Introduction: Special Section on Reliability-Aware Design and Analysis Methods for Digital Systems: From Gate to System Level

The fourteen articles in this special section represent world-leading current research into reliability-aware design methods for digital systems and provide interesting and valuable insights into current and future trends in the considered research areas. The focus on these articles is on investigating novel solutions for the reliability-aware design and analysis in digital systems, comprising a large number of issues and aspects (e.g. fault tolerance techniques, circuit aging and security), focusing on various architectures and devices (such as combinatorial circuits, memories, NoCs or FPGAs), and acting at different levels of abstraction (from circuit level to system level).

Reliability Aware Design and Lifetime Management of Computing Platforms

Meeting reliability targets with viable costs in the nanometer landscape become a significant challenge, requiring to be addressed in an unitary manner from design to run time. To this end, we propose a holistic reliability-aware design and lifetime management framework concerned (i) at design time, with providing a reliability enhanced adaptive architecture fabric, and (ii) at run time, with observing and dynamically managing fabric's wear-out profile such that user defined Quality-of-Service requirements are fulfilled, and with maintaining a full-life reliability log to be utilized as auxiliary information during the next IC generation design. After introducing our framework and the general philosophy behind it we delve into its key components. Specifically, we first introduce design time transistor and circuit level aging models, which provide the foundation for a 4-dimensional Design Space Exploration (DSE) meant to identify a reliability optimized circuit realization compliant with area, power, and delay constraints. Subsequently, to enable the creation of a low cost but yet accurate fabric observation infrastructure, we propose a methodology to minimize the number of aging sensors to be deployed in a circuit and identify their location, and introduce a sensor design able to directly capture circuit level amalgamated effects of concomitant degradation mechanisms. Furthermore, to make the information collected from sensors meaningful to the run-time management framework we introduce a circuit level model that can estimate the overall circuit aging and predict its End-of-Life based on imprecise sensors measurements, while taking into account the degradation nonlinearities. Finally, to provide more DSE reliability enhancement options we focus on the realization of reliable processing with unreliable components, and propose a methodology to obtain Error Correction Codes protected data processing units with an output error rate smaller than the fabrication technology gate error rate.

A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level

In the past few years, Time-Dependent Variability has become a subject of growing concern in CMOS technologies. In particular, phenomena such as Bias Temperature Instability, Hot-Carrier Injection and Random Telegraph Noise can largely affect circuit reliability. It becomes therefore imperative to develop reliability-aware design tools to mitigate their impact on circuits. To this end, these phenomena must be first accurately characterized and modeled. And, since all these phenomena reveal a stochastic nature for deeply-scaled integration technologies, they must be characterized massively on devices to extract the probability distribution functions associated to their characteristic parameters. In this work, a complete methodology to characterize these phenomena experimentally, and then extract the necessary parameters to construct a Time-Dependent Variability model, is presented. This model can be used by a reliability simulator.

Reliability-Aware Design Space Exploration for Fully Integrated RF CMOS PA

A design for reliability approach is proposed for fully integrated RF CMOS class A-to-C power amplifiers. Reliability hazards like time dependent dielectric breakdown and hot carrier injection are mapped into the design space, including the expected parametric degradation of the circuit, by fitting widely accepted models to experimental degradation results on the target technology. A prototype amplifier was used to validate RF degradation models and their impact on the output power degradation under accelerated stress. The methodology is based on a design space exploration of the highest efficiency designs attainable in a target technology. Electrical characteristics of passives and transistors are considered through look-up tables. The proposed approach allows to reduce the full universe of available designs to those that are specification and reliability compliant, avoiding a simulator-in-the-loop approach. A test case for a 3 dBm output power amplifier from the design space shows good agreement between predictions and SPICE simulations, including projected parametric degradation due to hot carrier injection.

An Analytical Model for Hot Carrier Induced Long-Term Degradation in Power Amplifiers

Degradation of power amplifier (PA), being a main part of a transceiver chain, affects the overall performance of a transceiver. This article reports, for the first time, an analytical reliability model of the hot-carrier injection (HCI) induced degradation in silicon-based PAs. HCI causes substrate current which is used to develop the proposed model. This model fits very well the simulation results of RelXpert, which is a well-established reliability simulation tool. This model predicts circuit degradation as a function of conduction angle and is valid for the different classes of PAs. With this model, a new approach for “reliability aware design” for PA design is developed and a tradeoff between PA performance and reliability is introduced.

Are CNNs Reliable Enough for Critical Applications? An Exploratory Study

Resource-constrained CNN implementations are subject to various reliability threats. This article provides an exploratory study investigating the impact of faults (soft errors modeled as bit flips) across the parameters of CNNs and the impact on the CNN weights, which can be used to create reliability-aware design guidelines. —Theocharis Theocharides, University of Cyprus —Muhammad Shafique, Technische Universitat Wien

Design for reliability of generic sensor interface circuits

Numerous applications require the use of robust and reliable integrated circuits. In order to develop such circuits, a wide variety of influences need to be considered and also compensated if necessary. For a complete consideration of all reliability issues, the circuit has to be investigated on different levels of abstraction and together with the complete overlying system. These requirements are addressed in this work by using cross-layer design methods for the development of a generic sensor interface as an example for a complex integrated circuit. During the development, a reliability-aware design is used and major physical effects are taken into account, which alter the overall behavior of the system. Furthermore, modeling techniques are applied to port influences and circuit components from one level of abstraction to another. Possible countermeasures and compensation techniques for a reliable circuit design are also analyzed on transistor and system level. The result is a sensor interface circuit, which can be used to investigate all effects of interest and suitable countermeasures on different abstraction levels.

WARM: Workload-Aware Reliability Management in Linux/Android

With CMOS scaling beyond 14 nm, reliability is a major concern for IC manufacturers. Reliability-aware design has a non-negligible overhead and cannot account for user experience in mobile devices. An alternative is dynamic reliability management (DRM), which counteracts degradation by adapting the operating conditions at runtime. In this paper, for the first time we formulate DRM as an optimization problem that accounts for reliability, temperature and performance. We develop an optimal policy for multicores using convex optimization, and show that it is not feasible to implement on real systems. For this reason, we propose workload-aware reliability management (WARM), a fast DRM technique adapting to diverse workload requirements to trade reliability and user experience. WARM is implemented and tested on a real Android device. WARM approximates the solution of the convex solver within 5% on average, while executing more than $400 {\times }$ faster. WARM integrates a thermal controller that allocates tasks to meet thermal constraints. This is required since degradation strongly depends on temperature. We show that WARM meets temperature constraints within 5% in 87.5% more cases than the state-of-the-art. We show that WARM task allocation achieves up to one year lifetime improvement for a multicore platform. It can achieve up to 100% of performance improvement on cluster architectures, such as big.LITTLE, while still guaranteeing the reliability target. Finally, we show that it achieves performance in the 4% of the maximum for a broad range of a applications, while meeting the reliability constraints.

Reliability-Aware Circuit Design Methodology for Beyond-5G Communication Systems

This paper focuses on efficient reliability analysis methodologies applicable for beyond-5G communication systems demonstrated on prospective terahertz (THz) technologies. Recently, a lot of the research interests have grown on optoelectronic integration which requires simultaneous management of electronic and optical modules. These technologies are evolving very rapidly, providing higher complexity, thereby increasing their susceptibility to stress environments (i.e., mutual self-heating) and finally requiring both robustness assessment and lifetime prediction under different operating conditions. Consequently, long-time reliability is a major issue. Extensive reliability assessment needs novel design methodologies that can provide reliability-aware optimization at the design level. This review discusses an extensive physics-based methodology for reliability prediction and analysis of degradation mechanisms in integrated-circuit technologies. Circuit-level design and optimization methodologies are illustrated by taking into account reliability-aware design techniques. Application examples and results are presented for an InP DHBT process, a viable technological solution for beyond-5G and THz applications.

Aging signature properties and an efficient signature determination tool for online monitoring

Increased reliability problems in deep sub-micron CMOS technologies have led to a dramatic decrease of lifetime of analog integrated circuits. To palliate this problem, several reliability-aware design approaches have been developed. Reconfigurable circuit design is one of those approaches, which is based on reconfiguring the circuit considering degradation in circuit performances. Sense & React (S & R) approach is the well-known reconfigurable design approach, where degradation in circuit performances are sensed and a pre-established recovery operation is applied to heal the circuit. In practice, indirect measurements are preferred during sense operation, in which electrical quantities are measured in order to determine time to recovery. Determination of the time to recover is the most critical part of a S & R system. One or more circuit variables are selected out of all measurable circuit quantities. The selected signature should have some attributes to be used as the aging signature to reduce the measurement cost. However, efficient aging signature properties have not been defined in the literature yet. Moreover, the designer determines the aging signature manually by performing an iterative search and evaluation on aging simulation results, and there is no tool to ease this time consuming process. This paper clearly describes the aging signature properties and proposes an automatic signature selection tool that determines the most efficient signature for sense operation.

Reliability-aware design for programmable QCA logic with scalable clocking circuit

The limitations of complementary metal---oxide---semiconductor (CMOS) technology on the nanoscale will prevent continuation of the current scaling trends in very large-scale integration (VLSI). Quantum-dot cellular automata (QCA) are one of the emerging nanotechnologies, conceived as a viable alternative to CMOS circuits, offering exceptionally high integration density, impressive switching frequency, and remarkably low power characteristics. However, fabrication issues and susceptibility to high error rates have raised many questions regarding this technology, leading to the search for efficient and scalable methods for design of QCA circuits. In this regard, this work targets a generic, reliable and programmable (RP) architecture for QCA with hybrid cell orientation. An efficient, easily manufacturable, and scalable clocking scheme is proposed towards the design of fault-tolerant QCA architectures. The functionality and defect tolerance of a five-input majority voter with RP structure (RMV) are investigated under cell deposition defects. Simulation results demonstrate that the proposed RP structure is more reliable than the conventional design. Besides reliability, the most striking characteristic of this logic is that it is completely programmable to perform various logic functions, reducing the requirement for disparate logic for large circuits. Comprehensive analysis of its programmable feature is applied to achieve a full adder, which extends its reliability to circuit level. The design of the QCA layout, as well as functional verification of the proposed design, is performed using QCADesigner.

RELSPEC: a framework for reliability aware design of component based embedded systems

With the increase in the complexity of safety-critical embedded applications, the reliability analysis of such systems have also become increasingly difficult. For such complex system specifications, if the reliability provisions are declared upfront in the design flow then the overall system level reliability can be easily inferred given that the system components satisfy their individual reliability requirements. Moreover, such an early-stage specification and analysis paves newer and scalable ways for synthesis of reliable systems. This paper develops a reliability specification and analysis framework, RELSPEC, which enables system level reliability analysis at an early-stage of design by leveraging automatically constructed intermediate probabilistic models of the system. In addition to this, we provide a mechanized method of system synthesis with the objective of satisfying a target reliability value for the overall system. To this end, we explore the application of existing optimization methods and also provide domain specific techniques which outperform such existing methods. Experiments over a few automotive case-studies show the efficacy of this methodology.

Reliability Tradeoffs in Design of Volatile and Nonvolatile Caches

Researchers have explored both volatile memories (e.g., SRAM and embedded DRAM) and nonvolatile memories (NVMs, such as resistive RAM) for design of on-chip caches. However, both volatile and nonvolatile memories present unique reliability challenges. NVMs are immune to radiation-induced soft errors, however, due to their limited write endurance, they are vulnerable to hard errors under nonuniform write distribution. By contrast, SRAM has high write endurance but is susceptible to soft errors due to cosmic radiation. SRAM–NVM hybrid caches and the management techniques for them aim to bring the best of SRAM and NVM together, however, the reliability implications of them have not been well understood. In this paper, we show that there are inherent tradeoffs in improving resilience to hard and soft errors in hybrid caches such that mitigating one may result in aggravating another. We confirm this by experiments with two recent hybrid cache management techniques. We also re-examine cache design trends in modern processors from reliability perspective. This paper provides valuable insights to system developers for making reliability-aware design decisions.

Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology

We investigate stochastic and deterministic reliability problems in the hybrid magnetic tunnel junction (MTJ)/MOS circuit which is implemented with ultra thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) technology. A spin torque transfer (STT) magnetic flip-flop (MFF) is designed with ultra wide voltage range, with 0.5V to 1.2V sense/read voltage, and 0.95V to 2V writing voltage, by using an industrial 28nm design kit and a physics-based STT-MTJ compact model. MFF performance can be improved with forward body bias (FBB) technology. The reliability-aware study shows that variability induced read/write failure is more dominant compared with aging induced degradation. Reliability-aware design of STT-MFF is discussed by proper selection of operation voltage.

Cross-layer investigation of continuous-time sigma–delta modulator under aging effects

In order to achieve reliability study in large and complex analog and mixed signal (AMS) circuits and systems, it is required to develop effective reliability-aware design methodologies and exploration tools. This paper discusses two aging mechanisms: hot carrier injection (HCI) and negative bias temperature instability (NBTI) and their effect on 65nm CMOS integrated circuits and systems (ICs). We propose an aging-aware cross-layer approach to comprehensively evaluate aging induced performance degradation at the abstraction (system) level. This approach is composed by hierarchical aging analysis at transistor/circuit level, block failure analysis at abstraction level and system-level aging considerations, which can essentially highlight sensitive blocks for circuit designers. This approach is demonstrated with a continuous-time (CT) sigma–delta (ΣΔ) modulator. Analog loop filter and clock distributor are studied with failure boundary and transistor level aging simulation. The aging investigation approach reports system level aging-aware consideration of these building blocks. Results show that amplifiers in analog loop filter have enough margin to cope with aging induced degradations. However, aging risk exists in clock circuits, especially when implementing with high Vt transistors. NBTI induced clock jitter from clock distributor can influence clocked block in CT ΣΔ modulator and degrade signal-to-noise ratio (SNR).

Reliability-Aware Design Flow for Silicon Photonics On-Chip Interconnect

Intercore communication in many-core processors presently faces scalability issues similar to those that plagued intracity telecommunications in the 1960s. Optical communication promises to address these challenges now, as then, by providing low latency, high bandwidth, and low power communication. Silicon photonic devices presently are vulnerable to fabrication and temperature-induced variability. Our fabrication and measurement results indicate that such variations degrade interconnection performance and, in extreme cases, the interconnection may fail to function at all. In this paper, we propose a reliability-aware design flow to address variation-induced reliability issues. To mitigate effects of variations, limits of device design techniques are analyzed and requirements from architecture-level design are revealed. Based on this flow, a multilevel reliability management solution is proposed, which includes athermal coating at fabrication-level, voltage tuning at device-level, as well as channel hopping at architecture-level. Simulation results indicate that our solution can fully compensate variations thereby sustaining reliable on-chip optical communication with power efficiency.

A framework for reliability-aware embedded system design on multiprocessor platforms

This paper presents a model-driven framework that provides a tool-supported design flow for fault-tolerant embedded systems. Its system models comprise abstract descriptions of the application and the underlying execution platform. They provide the input to our analysis and optimization techniques that enable the automated exploration of design alternatives for applications with reliability requirements. The automated generation of source code and platform configuration files speeds up the development process. Our contribution is to advance reliability-aware design further into practice by providing an integrated tool framework and removing unrealistic assumptions in the analyzes. The case studies demonstrate the effectiveness of our approach.