Reliability-aware Circuit Design Research Articles

Aging-Aware Gate-Level Modeling for Circuit Reliability Analysis

Due to severer transistor aging at nanoscale, circuit design margin becomes extremely tight for advanced technology nodes. Thus, reliability-aware circuit design is urgently needed. In this article, a new framework to perform aging-aware static timing analysis (STA) is presented for reliability analysis. The key parts of aging-aware STA flows are workload analysis and aged delay/transition calculation. For the workload analysis, a new analytical stress probability (SP) calculation model is proposed, which considers the floating effect and signal correlations. For aged delay/transition calculation, a new aging-aware model is developed, which is accessible to large industrial libraries. The results show that the proposed model achieves high accuracy in the degradation estimation and aged-path-delay calculation. Due to its high accuracy and scalability, the proposed framework is a promising solution that is compatible with commercial Electronic Design Automation (EDA) tools.

Hot Carrier Degradation-Induced Dynamic Variability in FinFETs: Experiments and Modeling

In this article, the dynamic variability induced by hot carrier degradation (HCD) in FinFETs is studied with decomposing the variation contributions of multiple types of traps. The nonlinear relationship of $\mu - \sigma ^{{2}}$ ( $\Delta {V}_{\,\text {th}}$ ) are newly observed in both n- and p-type FinFETs. A multitrap-based HCD variation model is proposed and verified in FinFETs. The impacts of HCD variations on the static random-access memory (SRAM) read/write stability are also demonstrated with the circuit simulation. The results are beneficial for the reliability-aware circuit design against HCD variability particularly for FinFET-based circuits.

Reliability analysis of BiCMOS SiGe:C technology under aggressive conditions for emerging RF and mm-wave applications: proposal of reliability-aware circuit design methodology

AbstractIn this contribution, the impact of extreme environmental conditions in terms of energy-level radiation of protons on silicon–germanium (SiGe)-integrated circuits is experimentally studied. Canonical representative structures including linear (passive interconnects/antennas) and non-linear (low-noise amplifiers) are used as carriers for assessing the impact of aggressive stress conditions on their performances. Perspectives for holistic modeling and characterization approaches accounting for various interaction mechanisms (substrate resistivity variations, couplings/interferences, drift in DC and radio frequency (RF) characteristics) for active samples are down to allow for optimal solutions in pushing SiGe technologies toward applications with harsh and radiation-intense environments (e.g. space, nuclear, military). Specific design prototypes are built for assessing mission-critical profiles for emerging RF and mm-wave applications.

Versatile Compact Model for Graphene FET Targeting Reliability-Aware Circuit Design

In this paper, we report on the development of a versatile compact model for graphene FETs (GFETs). Aging studies have been performed on the GFETs via bias stress measurements and aging laws were implemented in the compact model, including failure mechanisms in the GFETs. The failure mechanisms are identified to be originated from the generation of traps and interface states causing a shift in the transfer characteristics and mobility degradation, respectively. For the development of the aging compact model, the trap density is implemented in the prestress compact model to modulate the channel potential. Moreover, the interface state generation is implemented to reflect on the modification of the source/drain access region charges. The implemented aging model is compared with reported bias-stress measurement results as well as the aging measurements carried out on chemical vapor deposition GFETs which show a very good agreement.

RTN and BTI in nanoscale MOSFETs: A comprehensive statistical simulation study

This paper presents a thorough statistical investigation of random telegraph noise (RTN) and bias temperature instabilities (BTIs) in nanoscale MOSFETs. By means of 3D TCAD ‘atomistic’ simulations, we evaluate the statistical distribution in capture/emission time constants and in threshold voltage shift (ΔVT) amplitudes due to single trapped charge, comparing its impact on RTN and BTI. Our analysis shows that the individual BTI ΔVT steps are distributed identically as the RTN ΔVT steps. However, the individual traps in a device cannot be considered as uncorrelated sources of noise because their mutual interaction is fundamental in determining the dispersion of capture/emission time constants in BTI simulation. Further, we show that devices strongly affected by RTN are not necessarily strongly affected by BTI (and vice versa), revealing the uncorrelated nature of these two reliability issues. The presented results are of utmost importance for profoundly understanding the differences and similarities in the statistical behavior of RTN and BTI phenomena and assisting a reliability-aware circuit design.