Aging-Aware Gate-Level Modeling for Circuit Reliability Analysis

Abstract

Due to severer transistor aging at nanoscale, circuit design margin becomes extremely tight for advanced technology nodes. Thus, reliability-aware circuit design is urgently needed. In this article, a new framework to perform aging-aware static timing analysis (STA) is presented for reliability analysis. The key parts of aging-aware STA flows are workload analysis and aged delay/transition calculation. For the workload analysis, a new analytical stress probability (SP) calculation model is proposed, which considers the floating effect and signal correlations. For aged delay/transition calculation, a new aging-aware model is developed, which is accessible to large industrial libraries. The results show that the proposed model achieves high accuracy in the degradation estimation and aged-path-delay calculation. Due to its high accuracy and scalability, the proposed framework is a promising solution that is compatible with commercial Electronic Design Automation (EDA) tools.