Regular Iterative Algorithms Research Articles

Compact modular multiplier design for strong security capabilities in resource-limited Telehealth IoT devices

Telehealth is an emerging model of delivering quality health to remote communities and stay-at-home users. This is motivated by the rising health care costs and by the benefits of many patients staying at home as opposed to extended hospital stays. Telehealth relies on IoT technology, but IoT devices present the weakest security link to the system. The challenge is to implement strong security capabilities in resource-limited IoT devices. This justifies the use of elliptic curve cryptography (ECC) over the other traditional and resource-consumed approaches such as RSA. Efficient modular multiplication is a basic operation needed for ECC systems. Therefore, the compact and efficient implementation of this operation will significantly affect the performance of ECC in resource-limited applications. This work presents a compact serial-in/serial-out word-based systolic implementation of modular multiplication. The proposed structure is derived using a formal and systematic technique for mapping regular iterative algorithms (RIA) onto processor arrays. The proposed methodology enables control of the processor array workload as well as the workload of each processing element. Controlling the processor word size allows control of system speed, latency, and area. The proposed processor structure saves area and energy consumption by a factor up to 96.3% and 98.5%, respectively.

Compact Finite Field Multiplication Processor Structure for Cryptographic Algorithms in IoT Devices with Limited Resources.

The rapid evolution of Internet of Things (IoT) applications, such as e-health and the smart ecosystem, has resulted in the emergence of numerous security flaws. Therefore, security protocols must be implemented among IoT network nodes to resist the majority of the emerging threats. As a result, IoT devices must adopt cryptographic algorithms such as public-key encryption and decryption. The cryptographic algorithms are computationally more complicated to be efficiently implemented on IoT devices due to their limited computing resources. The core operation of most cryptographic algorithms is the finite field multiplication operation, and concise implementation of this operation will have a significant impact on the cryptographic algorithm’s entire implementation. As a result, this paper mainly concentrates on developing a compact and efficient word-based serial-in/serial-out finite field multiplier suitable for usage in IoT devices with limited resources. The proposed multiplier structure is simple to implement in VLSI technology due to its modularity and regularity. The suggested structure is derived from a formal and systematic technique for mapping regular iterative algorithms onto processor arrays. The proposed methodology allows for control of the processor array workload and the workload of each processing element. Managing processor word size allows for control of system latency, area, and consumed energy. The ASIC experimental results indicate that the proposed processor structure reduces area and energy consumption by factors reaching up to 97.7% and 99.2%, respectively.

Optical coherence elastography of bilayer soft tissue based on harmonic surface wave spectroscopy

Diseases often initiate from a certain layer of the biological tissue, thus simultaneous measurement of the elastic modulus of each layer is important for early diagnosis and treatment of various diseases. A surface wave spectroscopy (SWS) optical coherence elastography (OCE) technique based on harmonic wave excitation was proposed. An actuator consisting of a piezoelectric stack with a pin was designed to generate harmonic surface waves. A B-mode OCT data acquisition and phase analysis method was proposed to image the wave forms, and calculate the surface wave velocity. By exciting the sample with different frequencies, the surface wave dispersion curves were obtained. A total variation (TV) regularization iterative algorithm was proposed to obtain the elastic modulus distribution along the depth. Effectiveness of the proposed method was evaluated by both finite element simulation and experimental measurement of a bi-layer phantom. The mechanically driven harmonic wave actuation based OCE method is simple and cost-effective in experimental setup. Based on B-mode OCT scans, data analysis can be very fast, which is possible to realize real-time elastography imaging. This study provides an effective method for biomechanical properties study of layered tissue.

Comparison of four deblurring methods for streak image of streak tube imaging lidar

In this study, the Richardson–Lucy (R–L) iteration, Tikhonov (T–K) regularization, and fast iterative shrinkage-thresholding algorithm (FISTA) are first used to deblur streak images. The deblur performances of these three methods are compared with that of Wiener deconvolution. The spatial resolutions of Wiener deconvolution, R–L iteration, T–K regularization, and FISTA improved from 9 mm to 4.5, 5, 5, and 5 mm, respectively. The root-mean-square errors (RMSE) of one -, two -, and three-plane targets decreased effectively using these three deblur methods. The R–L iteration performs the best in terms of the RMSE for the two-plane target. The effects of the parameters used in each method are investigated.

Fast self-adaptive regularization iterative algorithm for solving split feasibility problem

Split feasibility problem (SFP) is to find a point which belongs to one convex set in one space, such that its image under a linear transformation belongs to another convex set in the image space. This paper deals with a unified regularized SFP for the convex case. We first construct a self-adaptive regularization iterative algorithm by using Armijo-like search for the SFP and show it converges at a subliner rate of \begin{document}$ O(1/k) $\end{document} , where \begin{document}$ k $\end{document} represents the number of iterations. More interestingly, inspired by the acceleration technique introduced by Nesterov[ 12 ], we present a fast Armijo-like regularization iterative algorithm and show it converges at rate of \begin{document}$ O(1/k^{2}) $\end{document} . The efficiency of the algorithms is demonstrated by some random data and image debluring problems.

Simultaneous deblurring and iterative reconstruction of CBCT for image guided brain radiosurgery

One of the limiting factors in cone-beam CT (CBCT) image quality is system blur, caused by detector response, x-ray source focal spot size, azimuthal blurring, and reconstruction algorithm. In this work, we develop a novel iterative reconstruction algorithm that improves spatial resolution by explicitly accounting for image unsharpness caused by different factors in the reconstruction formulation. While the model-based iterative reconstruction techniques use prior information about the detector response and x-ray source, our proposed technique uses a simple measurable blurring model. In our reconstruction algorithm, denoted as simultaneous deblurring and iterative reconstruction (SDIR), the blur kernel can be estimated using the modulation transfer function (MTF) slice of the CatPhan phantom or any other MTF phantom, such as wire phantoms. The proposed image reconstruction formulation includes two regularization terms: (1) total variation (TV) and (2) nonlocal regularization, solved with a split Bregman augmented Lagrangian iterative method. The SDIR formulation preserves edges, eases the parameter adjustments to achieve both high spatial resolution and low noise variances, and reduces the staircase effect caused by regular TV-penalized iterative algorithms. The proposed algorithm is optimized for a point-of-care head CBCT unit for image-guided radiosurgery and is tested with CatPhan phantom, an anthropomorphic head phantom, and 6 clinical brain stereotactic radiosurgery cases. Our experiments indicate that SDIR outperforms the conventional filtered back projection and TV penalized simultaneous algebraic reconstruction technique methods (represented by adaptive steepest-descent POCS algorithm, ASD-POCS) in terms of MTF and line pair resolution, and retains the favorable properties of the standard TV-based iterative reconstruction algorithms in improving the contrast and reducing the reconstruction artifacts. It improves the visibility of the high contrast details in bony areas and the brain soft-tissue. For example, the results show the ventricles and some brain folds become visible in SDIR reconstructed images and the contrast of the visible lesions is effectively improved. The line-pair resolution was improved from 12 line-pair/cm in FBP to 14 line-pair/cm in SDIR. Adjusting the parameters of the ASD-POCS to achieve 14 line-pair/cm caused the noise variance to be higher than the SDIR. Using these parameters for ASD-POCS, the MTF of FBP and ASD-POCS were very close and equal to 0.7 mm−1 which was increased to 1.2 mm−1 by SDIR, at half maximum.

Non-smooth Hybrid Energy Functional Regularization Model for Image Reconstruction

For overcoming the shortcomings of total variation for image reconstruction, which easily smooth image texture, and produce lots of artificial edges, a non-smooth hybrid energy functional regularization model and iterative algorithm is proposed. Firstly, fitting term is described by L1 norm for blurred image by system and salt and pepper noise, regularization terms are described by fractional order bounded variation function semi-norm and L1 norm. Secondly, resorting to introduce auxiliary variables, the primal non-smooth energy functional regularization model without condition constraints is converted into energy functional regularization model with condition constraints, which is split into six easily computing sub-problems by the alternating direction method of multipliers (ADMM). Finally, alternating iterative six sub-problems, an improved image reconstruction algorithm is proposed. Numerical experiments show that the proposed model has advantages over several state-of-art approaches in terms of the reconstruction visual effect.

Image Restoration Using Gradient Iteration and Constraints for Band Extrapolation

Images obtained with optical microscopes are often blurred and corrupted by noise. Specially in wide-field microscopy, there is a strong out-of-focus blur in focal plane direction, caused mainly by a frequency loss in the acquisition process. In order to restore these images it is important to use non-linear methods and relevant prior knowledge as constraints. In this paper, we propose a projection onto convex sets framework using a sequence of prototype images inspired by the Richardson–Lucy iterative algorithm. Within this framework it is possible to use constraints while restoring the image, during the iterations. We prove that the iterative method can be implemented as a gradient iteration, followed by a sequence of projections onto constraint sets. Moreover, we performed experiments using the techniques in order to improve restoration. The results showed a better restoration of frequencies, an improved focal plane restoration and a better contrast when compared with the regular iterative restoration algorithm.

STEADY ESTIMATION ALGORITHMS OF THE DYNAMIC SYSTEMS CONDITION ON THE BASIS OF CONCEPTS OF THE ADAPTIVE FILTRATION AND CONTROL

Dynamic systems condition estimation regularization algorithms in the conditions of signals and hindrances statistical characteristics aprioristic uncertainty are offered. Regular iterative algorithms of strengthening matrix factor elements of the Kalman filter, allowing to adapt the filter to changing hindrance-alarm conditions are developed. Steady adaptive estimation algorithms of a condition vector in the aprioristic uncertainty conditions of covariance matrixes of object noise and the measurements hindrances providing a certain roughness of filtration process in relation to changing statistical characteristics of signals information parameters are offered. Offered practical realization results of the dynamic systems condition estimation algorithms are given at the adaptive management systems synthesis problems solution by technological processes of granulation drying of an ammophos pulp and receiving ammonia.

High Performance Systolic Architecture by Evolutionary Design

This paper focuses on design of systolic architecture and by the application of evolutionary programming to achieve 100% HUE (Hardware Utilization Efficiency) for space representation containing delays in systolic design. Heuristic method involves EP (Evolutionary Programming) to solve the problems where the solution is in large search space. Using EP, we are able to find the number of different solutions for designing the systolic architecture for regular iterative algorithms. From which the user can choose any design of his choice according to his application.

A vector regularization method to solve linear inverse problems

The linear inverse problem is discretized to be an n-dimensional ill-posed linear equations system . In the present paper, an invariant manifold defined in terms of the square norm of a residual vector is used to derive an iterative algorithm with a fast descent direction , which is close to, but not exactly equal to, the best descent direction . The matrix is obtained by using a vector regularization method together with a matrix conjugate gradient method to find the right inversion of : . The vector regularization iterative algorithm is proven to be Lyapunov stable, and the direct inversion method with solution expressed by converges fast. The accuracy and efficiency of them are verified through the numerical tests of linear inverse problems under a large random noise.

An Alternative Regularization Method forEquilibrium Problems and Fixed Point ofNonexpansive Mappings

We introduce a new regularization iterative algorithm for equilibrium and fixed point problems of nonexpansive mapping. Then, we prove a strong convergence theorem for nonexpansive mappings to solve a unique solution of the variational inequality and the unique sunny nonexpansive retraction. Our results extend beyond the results of S. Takahashi and W. Takahashi (2007), and many others.

A NEW PLATFORM FOR THE IMPLEMENTATION OF REGULAR ITERATIVE ALGORITHMS INTO FPGAs

The implementation of regular iterative algorithms (RIAs) in important scientific fields such as image processing, computer arithmetic, cryptography and their implementation in processor arrays architectures, has been extensively studied over the last three decades. Numerous design methodologies and tools have been proposed, mostly targeting custom very large scale integration (VLSI) chips. The advent of field-programmable gate arrays (FPGAs) has attracted many researchers to incorporate previously acquired knowledge and experience in designing VLSI chips, to this new technology. This paper addresses the issue of the implementation of regular algorithms into FPGAs and presents a novel design tool for the implementation of RIAs, formulated as dependence graphs (DGs), on systolic arrays. Furthermore, a platform scheme for the systolic arrays hardware realization is proposed.

Nineteen ways of systolic matrix multiplication

In this paper, we have designed nineteen systolic arrays for matrix multiplication under the frame work of the systolic synthesis method using regular iterative algorithm (RIA) representation. Then we define different systolic array performance measures in order to evaluate the systolic designs. The performance of the designed systolic arrays is analysed in details and this allows the comparison among the different systolic designs.

A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays

This paper addresses the partitioning and scheduling problems in mapping multi-stage regular iterative algorithms onto fixed size distributed memory processor arrays. We first propose a versatile partitioning model which provides a unified framework to integrate various partitioning schemes such as "locally sequential globally parallel", "locally parallel globally sequential" and "multi-projection". To alleviate the run time data migration overhead--a crucial problem to the mapping of multi-stage algorithms, we further relax the widely adopted atomic partitioning constraint in our model such that a more flexible partitioning scheme can be achieved. Based on this unified partitioning model, a novel hierarchical scheduling scheme which applies separate schedules at different processor hierarchies is then developed. The scheduling problem is then formulated into a set of ILP problem and solved by the existing software package for optimal solutions. Examples indicate that our partitioning model is a superset of the existing schemes and the proposed hierarchical scheduling scheme can outperform the conventional one-level linear schedule.

Some new designs of 2-D array for matrix multiplication and transitive closure

We present some new regular iterative algorithms for matrix multiplication and transitive closure. With these algorithms, by spacetime mapping the 2-D arrays with 2N-1 and upper bound [(3N-1)/2] execution times for matrix multiplication can be obtained. Meanwhile, we can derive a 2-D array with 4N-2 execution rime for transitive closure based on the sequential Warshall-Floyd algorithm. All these new 2-D arrays for matrix multiplication and transitive closure have the advantages of faster and more regular than other previous designs. >

Design of efficient regular arrays for matrix multiplication by two-step regularization

A two-step regularization method in which first permutation sequences and then broadcast planes are selected is proposed to design various regular iterative algorithms for matrix multiplication. The regular iterative algorithms are then spacetime mapped to regular arrays, such as mesh, cylindrical, two-layered mesh, and orbital arrays. The proposed method can be used to design regular arrays with execution time of less than N (problem size).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Assessing partitioning/ scheduling/storage trade-offs for regular iterative algorithms

The problem of partitioning systolic algorithms (a subclass of Regular Iterative Algorithms (RIA) has been studied by a number of researchers. One approach to partitioning the algorithm is to divide the index space into equivalence classes called blocks. The blocks are scheduled and placed on a processor array of a fixed size. This approach creates the need for auxiliary memory structures to store partial results and the need for control circuitry to direct the resulting non-uniform flow of data values within the array. The implementation of these structures and the means of comparing the cost of differences in the structures resulting from various partitioning and scheduling policies has been largely omitted in the literature. In this paper we offer a detailed model of Fixed Size Array Processors architectures. Using this model we may assess the trade-offs between auxiliary memory structure size, execution time, and control circuit complexity. The control circuits generate signals which determine the data flow through the array. We emphasize methods for controlling non-uniform data flow resulting from some partitionings of the index space. We show how to derive the control signals in such arrays from the determination of the index points. We also show how the translation of index points to control signals can be refined by a process of index pipelining which reduces the complexity of the control circuitry. Several partitioning and scheduling schemes for QR decomposition are evaluated to illustrate how the model may be used to determine a good partitioning/scheduling/storage configuration.

Data flow representation of iterative algorithms for systolic arrays

An algebraic representation is proposed for regular iterative algorithms that can be described as bundles of data flows with different wavefronts. A form corresponding to a geometric representation such as a dependence graph is obtained by modeling data flows with a generating function of a power series. The main attributes of systolic algorithms and arrays are revealed by a unique dataflow representation. This provides the ability to pipeline two or more systolic arrays solving different subproblems without intermediate buffering. An example is given to show a case in which the technique can be used. >

A VLSI design methodology for distributed arithmetic

Real-time signal processing requires fast computation of inner products. Distributed arithmetic is a method of inner product computation that uses table-lookup and addition in place of multiplication. Distributed arithmetic has previously been shown to produce novel and seemingly efficient architectures for a variety of signal processing computations; however the methods of design, analysis and comparison have been ad hoc. We propose a systematic method for synthesizing optimal VLSI architectures using distributed arithmetic. A partition of the inner product computation at the word and bit level produces a computation consisting of lookups and additions. We study two classes of algorithms to implement this computation, regular iterative algorithms and tree algorithms, each of which can be expressed in the form of a dependency graph. We use linear and nonlinear maps to assign computations to processors in space and time. Expressions are developed for the area, latency, period and arithmetic error for a particular partition and space/time map of the dependecy graph. We use these expressions to formulate a constrained optimization problem over a large class of architectures. We compare distributed arithmetic with more conventional methods for inner product computation and show how area, latency and period may be traded off while maintaining constant error.