Regular Data Structures Research Articles

Mnemosyne

New storage-class memory (SCM) technologies, such as phase-change memory, STT-RAM, and memristors, promise user-level access to non-volatile storage through regular memory instructions. These memory devices enable fast user-mode access to persistence, allowing regular in-memory data structures to survive system crashes. In this paper, we present Mnemosyne, a simple interface for programming with persistent memory. Mnemosyne addresses two challenges: how to create and manage such memory, and how to ensure consistency in the presence of failures. Without additional mechanisms, a system failure may leave data structures in SCM in an invalid state, crashing the program the next time it starts. In Mnemosyne, programmers declare global persistent data with the keyword "pstatic" or allocate it dynamically. Mnemosyne provides primitives for directly modifying persistent variables and supports consistent updates through a lightweight transaction mechanism. Compared to past work on disk-based persistent memory, Mnemosyne reduces latency to storage by writing data directly to memory at the granularity of an update rather than writing memory pages back to disk through the file system. In tests emulating the performance characteristics of forthcoming SCMs, we show that Mnemosyne can persist data as fast as 3 microseconds. Furthermore, it provides a 35 percent performance increase when applied in the OpenLDAP directory server. In microbenchmark studies we find that Mnemosyne can be up to 1400% faster than alternative persistence strategies, such as Berkeley DB or Boost serialization, that are designed for disks.

Mnemosyne

New storage-class memory (SCM) technologies, such as phase-change memory, STT-RAM, and memristors, promise user-level access to non-volatile storage through regular memory instructions. These memory devices enable fast user-mode access to persistence, allowing regular in-memory data structures to survive system crashes. In this paper, we present Mnemosyne, a simple interface for programming with persistent memory. Mnemosyne addresses two challenges: how to create and manage such memory, and how to ensure consistency in the presence of failures. Without additional mechanisms, a system failure may leave data structures in SCM in an invalid state, crashing the program the next time it starts. In Mnemosyne, programmers declare global persistent data with the keyword "pstatic" or allocate it dynamically. Mnemosyne provides primitives for directly modifying persistent variables and supports consistent updates through a lightweight transaction mechanism. Compared to past work on disk-based persistent memory, Mnemosyne reduces latency to storage by writing data directly to memory at the granularity of an update rather than writing memory pages back to disk through the file system. In tests emulating the performance characteristics of forthcoming SCMs, we show that Mnemosyne can persist data as fast as 3 microseconds. Furthermore, it provides a 35 percent performance increase when applied in the OpenLDAP directory server. In microbenchmark studies we find that Mnemosyne can be up to 1400% faster than alternative persistence strategies, such as Berkeley DB or Boost serialization, that are designed for disks.

Certified self-modifying code

Self-modifying code (SMC), in this paper, broadly refers to anyprogram that loads, generates, or mutates code at runtime. It is widely used in many of the world's critical software systems tosupport runtime code generation and optimization, dynamic loading and linking, OS boot loader, just-in-time compilation, binary translation,or dynamic code encryption and obfuscation. Unfortunately, SMC is alsoextremely difficult to reason about: existing formal verification techniques-including Hoare logic and type system-consistentlyassume that program code stored in memory is fixedand immutable; this severely limits their applicability and power. This paper presents a simple but novel Hoare-logic-like framework that supports modular verification of general von-Neumann machine code with runtime code manipulation. By dropping the assumption that code memory is fixed and immutable, we are forced to apply local reasoningand separation logic at the very beginning, and treat program code uniformly as regular data structure. We address the interaction between separation and code memory and show how to establish the frame rules for local reasoning even in the presence of SMC. Our frameworkis realistic, but designed to be highly generic, so that it can support assembly code under all modern CPUs (including both x86 andMIPS). Our system is expressive and fully mechanized. We prove itssoundness in the Coq proof assistant and demonstrate its power by certifying a series of realistic examples and applications-all of which can directly run on the SPIM simulator or any stock x86 hardware.

Interactive visual functional programming

An interactive graphical environment for supporting the development and use of Haskell applications programs is described. The environment, named Vital, is particularly intended for supporting the open-ended, incremental development style often preferred by non-specialist users in which successive steps of program development are motivated and informed by results so far obtained.Significant features of Vital include: the graphical display of data structures in a format defined by a datatype-indexed stylesheet, the way that evaluation of (possibly infinite) values is demand-driven by the action of the user scrolling around an unbounded workspace, and support for copy-and-paste graphical editing of data structures. This latter allows, for example, the user to modify a complex data structure by point-and-click operations, or to create (by functional evaluation) a regular data structure and then edit values or expressions into it. The effect of each editing operation is immediately reflected in the Haskell program source code.

Efficient Regular Data Structures and Algorithms for Dilation, Location, and Proximity Problems

Investigates data structures obtained by a recursive partitioning of the input domain into regions of equal size. One of the most well-known examples of such a structure is the quadtree, which is used in this paper as a basis for more complex data structures; we also provide multidimensional versions of the stratified tree of P. van Emde Boas (1997). We show that, under the assumption that the input points have limited precision (i.e. are drawn from an integer grid of size u), these data structures yield efficient solutions to many important problems. In particular, they allow us to achieve O(log log u) time per operation for finding the dynamic approximate nearest neighbor (under insertions and deletions) and the exact online closest pair (under insertions only) in any constant dimension. They allow O(log log u) point location in a given planar shape or in its expansion (dilation by a ball of a given radius). Finally, we provide a linear-time (optimal) algorithm for computing the expansion of a shape represented by a quadtree. This result shows that the spatial order imposed by this regular data structure is sufficient to optimize the dilation by a ball operation.

A Comparison of Implicitly Parallel Multithreaded and Data-Parallel Implementations of an Ocean Model

Two parallel implementations of a state-of-the-art ocean model are described and analyzed: one is written in the implicitly parallel language Id for the Monsoon multithreaded dataflow architecture, and the other in data-parallel CM Fortran for the CM-5. The multithreaded programming model is inherently more expressive than the data-parallel model but is not especially adapted to regular data structures common to many scientific codes. One goal of this study is to understand what, if any, are the performance penalties of multithreaded execution when implementing a program that is well suited for data-parallel execution. To avoid technology and machine configuration issues, the two implementations are compared in terms of overhead cycles perrequiredfloating point operation. When flows in complex geometries typical of ocean basins are simulated, the data-parallel model only remains efficient if redundant computations are performed over land. The generality of the Id programming model, however, allows one to easily and transparently implement a parallel code that computes only in the ocean. When ocean basins with complex and irregular geometry are simulated the normalized performance on Monsoon is comparable with that of the CM-5. For more regular geometries that map well to the computational domain, the data-parallel approach proves to be a better match. We conclude by examining the extent to which clusters of mainstream symmetric multiprocessor (SMP) systems offer a scientific computing environment which can capitalize on and combine the strengths of the two paradigms.

Visibility analysis on a massively data‐parallel computer

Visibility analysis algorithms use digital elevation models (DEMs), which represent terrain topography, to determine visibility at each point on the terrain from a given location in space. This analysis can be computationally very demanding, particularly when manipulating high resolution DEMs accurately at interactive response rates. Massively data-parallel computers offer high computing capabilities and are very well-suited to handling and processing large regular spatial data structures. In the paper, the authors present a new scanline-based data-parallel algorithm for visibility analysis. Results from an implementation onto a MasPar massively data-parallel SIMD computer are also presented.

Visibility analysis on a massively data-parallel computer

Visibility analysis algorithms use digital elevation models (DEMs), which represent terrain topography, to determine visibility at each point on the terrain from a given location in space. This analysis can be computationally very demanding, particularly when manipulating high resolution DEMs accurately at interactive response rates. Massively data-parallel computers offer high computing capabilities and are very well-suited to handling and processing large regular spatial data structures. In the paper, the authors present a new scanline-based data-parallel algorithm for visibility analysis. Results from an implementation onto a MasPar massively data-parallel SIMD computer are also presented.

Portable parallelizing Fortran compiler

The Portable Parallelizing Fortran Compiler (PPFC) is an additional component for the portable programming environment developed in Tel-Aviv University for scientific code. This environment supports portable and efficient programming of diverse MIMD multiprocessors, both distributed- and shared-memory. Till now this environment has consisted of two tools: the Virtual Machine for MultiProcessors (VMMP) and the Portable Parallelizing Pascal compiler (P3C). We have added the PPFC which is an automatic parallelizer compiler for the Fortran language. The compiler is fully automatic (does not require additional declarations to assist parallelization), which is characterized by loops operating on regular data structures, and produces efficient and portable code for a variety of multiprocessors from the same serial code. The parallel implementation uses the VMMP, which is a software package that provides a coherent set of services for explicitly parallel application programs running on diverse MIMD multiprocessors. VMMP is intended to simplify parallel program writing and to promote portable and efficient programming. The PPFC parallelized 12 out of the 24 Livermore Loops. It was also applied to parallelize all the 14 Fortran application programs that where parallelized by the P3C and achieved the same speed-ups and efficiencies. In most examples the PPFC achieved high speed-ups and efficiencies on all target multiprocessors. The PPFC emphasizes efficiency and code portability. Although PPFC employs a relatively simple data flow analysis, it produces efficient code for various widely used application programs.

Portable parallelizing Fortran compiler

The Portable Parallelizing Fortran Compiler (PPFC) is an additional component for the portable programming environment developed in Tel-Aviv University for scientific code. This environment supports portable and efficient programming of diverse MIMD multiprocessors, both distributed- and shared-memory. Till now this environment has consisted of two tools: the Virtual Machine for MultiProcessors (VMMP) and the Portable Parallelizing Pascal compiler (P3C). We have added the PPFC which is an automatic parallelizer compiler for the Fortran language. The compiler is fully automatic (does not require additional declarations to assist parallelization), which is characterized by loops operating on regular data structures, and produces efficient and portable code for a variety of multiprocessors from the same serial code. The parallel implementation uses the VMMP, which is a software package that provides a coherent set of services for explicitly parallel application programs running on diverse MIMD multiprocessors. VMMP is intended to simplify parallel program writing and to promote portable and efficient programming. The PPFC parallelized 12 out of the 24 Livermore Loops. It was also applied to parallelize all the 14 Fortran application programs that where parallelized by the P3C and achieved the same speed-ups and efficiencies. In most examples the PPFC achieved high speed-ups and efficiencies on all target multiprocessors. The PPFC emphasizes efficiency and code portability. Although PPFC employs a relatively simple data flow analysis, it produces efficient code for various widely used application programs.

Correct translation of data parallel assignment onto array processors

Abstract Two models of computation which are suitable for the description of parallel scientific calculations on large data structures are presented. Data parallel assignment is a construct which may be used to specify the application of a set of order independent fine grained operations to a regular data structure. It is formulated in a machine independent way and, consequently, is suitable for implementation on a range of novel parallel architectures. An operational model of data parallel computation is provided by specifying a model array processor. The specification captures the essential features of the class of array processors and it may be instantiated in order to define a particular machine. A formal operational semantics of data parallel assignment is given for the model array processor. The translation mechanism is shown to be correct. The exercise clarifies some of the issues in deciding whether or not it is feasible to translate data parallel assignment directly onto array processor architectures.

Cache tiling for high performance morphological image processing

Morphological image analysis is a technique of processing images through shape characteristics (Jain 1989). Because images are regular data structures, morphology algorithm's memory access patterns are predictable. By using read and write patterns, we derive a model of processing to examine inefficiencies in cache processing. We then develop a cache architecture for windowed processing that reduces cache thrashing. Our caching technique, cache tiling, improves efficiency dramatically for small caches independent of compiler optimizations. Programs are not affected, providing a transparent solution to improve caching. A system code, compilers, or profiling programs can determine the blocking necessary for the best performance. An analytical model for morphological processing's memory characteristics is presented that provides for exact cache analysis and prediction. The analytical model is compared to address traces to validate the model. Other algorithms such as inner product, matrix multiplication, and convolution also benefit from the architecture presented herein.

Portable, parallelizing Pascal compiler

The structure and implementation of P/sup 3/C, a compiler that uses relatively simple parallelization techniques to produce highly efficient code for both shared-memory and distributed-memory MIMD multiprocessors, are discussed. P/sup 3/C is a fully automatic, portable parallelizing Pascal compiler for scientific code, which is characterized by loops operating on regular data structures. P/sup 3/C compiles the same source code to all target machines without modification. P/sup 3/C gives an accurate estimate about whether the parallel code will actually reduce execution time over serial code, taking into account the associated overhead. It derives the estimate by statically analyzing the program at compile time, referring to a table of the target machine's parameters. Speedups of up to 24 have been achieved on a Sequent Symmetry with 25 active processors. The estimated speedup was within 8% of the actual figure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Block Band Matrix Subspace Iteration

Abstract: For a microcomputer user in civil engineering, the. major factor of concern is not necessarily the computing time but the incore memory. It is particularly important for dynamic and nonlinear analyses. Solution techniques employing secondary memory to extend the capacity of a microcomputer in solving engineering problems are active research topics. There are many engineering problems which have regular data structures, e.g. tall buildings, long bridges, etc. Band matrix solution techniques are suitable for regular data structures. A partitioned matrix method is introduced for the engineering eigenvalue problem here. Static solutions are included as particular cases. FORTRAN listings are given.

Real-Time Collision Avoidance for Kinematically Redundant Manipulators

This paper presents a collision avoidance algorithm for kinematically redundant manipulators. The main interesting aspects of this algorithm are:•real-time application: if the time slot of the real time system is too short for computing the full algorithm, freedom of collision is guaranteed by a worst-case check•full 3-D features•general purpose: nearly all kinematic structures may be specified•robots and obstacles are treated similarly•regular data structures and algorithms: implementation on special hardware is possibleThe algorithm was implemented on a 68020 computer and tested by use of a robot simulation system.

Pipeline architectures for morphologie image analysis

The concepts of mathematical morphology provide some very powerful tools with which low-level image analysis can be performed. Low-level analysis, by its very nature, involves repeated computations over large, regular data structures. Parallelism appears to be a necessary attribute of a hardware system which can efficiently perform such image-analysis tasks, and there is a variety of forms that this parallelism can take. This paper gives a tutorial description of the basic morphological transformations and demonstrates how the basic morphological transformations can be implemented in the pipeline processing form of parallelism. Correspondingly, plausible designs for pipeline architectures are developed.

The Software-Cache Connection

This paper describes an adaptation of standard Fourier analysis techniques to the study of software-cache interactions. The cache is viewed as a black box boolean signal generator, where ones correspond to cache misses and zeros correspond to cache hits. The spectrum of this time sequence is used to study the dynamic characteristics of complex systems and workloads with minimal a priori knowledge of their internal organization. Line spectra identify tight loops accessing regular data structures, while the overall spectral density reveals the general structure of instruction localities.

A model for data structures and its applications. I

This paper presents a constructive model for data structures description based on the concept of data space defined as the Cartesian product of a name space and a value space. The subsets of name space are ordered by an a priori given selector function. The model is used for classification of data structures into regular (array-like), semiregular (key-ordered list-like) and irregular (threaded list-like) data structures. The notion of data storage structures induced by addressing mechanism is introduced and storage mapping functions are described using this concept together with the data structure model. The first part of the paper contains also some of the model applications to regular and semiregular data structure problems and a brief comparison withAlgol 68 treatment of regular data structures.

A real-time language for industrial process control

Industrial computer control systems require the economical production of efficient software including executive systems, maintenance programs, and both special and general purpose application programs for direct digital control. Moreover, the hardware configuration varies considerably from the single dedicated control computer to a general purpose multicomputer system. RTL, a real-time language developed cooperatively with industrial suppliers and users specifically for industrial control, is described with emphasis on those features peculiar to applications such as dedicated direct digital control, combined direct and supervisory control, operator interfaces, and interaction with plant management computer systems. The use of RTL for the production of special purpose executive systems and general purpose application programs for direct control, startup, etc., is emphasized. Details of the language discussed with examples include its file structure for communication of data bases between independent programs, and a variety of data types including character codes, strings, labels, lists, peripheral variables, and data structures. Peripheral variables are variables in the language associated with hard-ware features of the central processor and its input-output devices such as registers, interrupts, error indicators, and addresses all of which may be referenced in the language. Regular and peripheral variable data structures--combinations of different types of variables--are included and ease considerably the burden of real-time programming. The organization and performance of the existing compiler for RTL is explained.