Buffer Register Research Articles

Modified SHA1: A Hashing Solution to Secure Web Applications through Login Authentication

The modified SHA1 algorithm has been developed by expanding its hash value up to 1280 bits from the original size of 160 bit. This was done by allocating 32 buffer registers for variables A, B, C and D at 5 bytes each. The expansion was done by generating 4 buffer registers in every round inside the compression function for 8 times. Findings revealed that the hash value of the modified algorithm was not cracked or hacked during the experiment and testing using powerful online cracking tool, bruteforce and rainbow table such as CrackingStation and Rainbow Crack and bruteforcer which are available online thus improved its security level compared to the original SHA1.

Towards designing quantum reversible 32-bit MIPS register file

Reversible circuit design can be applied in various emerging technologies such as quantum computing. Since researchers have proposed many building blocks and designed small circuits (e.g., reversible full adder) already, it is the time to design large-scale reversible circuits. This paper proposes a novel quantum reversible 32-bit MIPS register file for quantum computer processors. It presents a reversible 5-to-32 decoder, 32 reversible buffer registers, and two reversible 32-to-1 multiplexers, too. The proposed reversible decoder block, namely GH-DEC, and the proposed reversible multiplexer block, namely GH-MUX, use the Feynman, Toffoli, and Fredkin gates. They have been designed by a minimum number of constant inputs, number of garbage outputs, and quantum cost. Besides, output expressions of all the circuits are simplified to enhance the performance of proposed quantum design, considerably. Comparison results show that the proposed reversible design surpasses the existing works in terms of the number of constant inputs, number of garbage outputs, and quantum cost.

Towards designing quantum reversible 32-bit MIPS register file

Reversible circuit design can be applied in various emerging technologies such as quantum computing. Since researchers have proposed many building blocks and designed small circuits (e.g., reversible full adder) already, it is the time to design large-scale reversible circuits. This paper proposes a novel quantum reversible 32-bit MIPS register file for quantum computer processors. It presents a reversible 5-to-32 decoder, 32 reversible buffer registers, and two reversible 32-to-1 multiplexers, too. The proposed reversible decoder block, namely GH-DEC, and the proposed reversible multiplexer block, namely GH-MUX, use the Feynman, Toffoli, and Fredkin gates. They have been designed by a minimum number of constant inputs, number of garbage outputs, and quantum cost. Besides, output expressions of all the circuits are simplified to enhance the performance of proposed quantum design, considerably. Comparison results show that the proposed reversible design surpasses the existing works in terms of the number of constant inputs, number of garbage outputs, and quantum cost.

OverCome: Coarse-Grained Instruction Commit with Handover Register Renaming

Coarse-grained instruction commit mechanisms enabled the effective size of the instruction window to be as large as possible by committing a group of instructions atomically. Within a group, the reorder buffer (ROB) and physical register file (PRF) entries are conservatively managed, and thus the instruction window can handle more in-flight instructions beyond the hardware limit. However, previous approaches have suffered from high storage requirements for managing group information and unbalanced lifetime of instruction window resources, i.e., the ROB and PRF. In this paper, we propose an OverCome microarchitecture based on a history-based approach to address these problems. First, OverCome retains the conservative allocation of the ROB regardless of the group size limit, thereby providing high scalability. Second, it handles the information of numerous groups with a low storage cost. These two techniques achieve a significant reduction in the pressure on the ROB; thus, a new bottleneck arises: the pressure on the PRF. To address this issue, we propose a novel register renaming technique to reduce the lifetime of physical registers to a large extent, by tightly coupling the early release and lazy allocation schemes. Thus, the proposed design strikes a balance between the ROB and PRF requirements. Detailed evaluation of the proposed techniques on a state-of-the-art superscalar processor shows that our proposals augment the effective size of the instruction window by more than $4\times$ 4 × , with a net overhead of less than 3 percent of the core area.

Modified SHA1: A Hashing Solution to Secure Web Applications through Login Authentication

The modified SHA1 algorithm has been developed by expanding its hash value up to 1280 bits from the original size of 160 bit. This was done by allocating 32 buffer registers for variables A, B, C and D at 5 bytes each. The expansion was done by generating 4 buffer registers in every round inside the compression function for 8 times. Findings revealed that the hash value of the modified algorithm was not cracked or hacked during the experiment and testing using powerful online cracking tool, bruteforce and rainbow table such as CrackingStation and Rainbow Crack and bruteforcer which are available online thus improved its security level compared to the original SHA1.

Memory of Subjects of Communication: The Structural and Functional Components

The essence of psychological theories of memory is highlighted in the article. It is proved that the memory of subjects of communication has a three-component structure: the sensory register, short-term and long-term memory. The specifics of the work of psychological mechanisms of each of its structural and functional components are revealed. Physical signs of new information items that are valuable to communication subjects, are transmitted to processing and preservation, and invaluable and unrecognized – are sent to the sensory register buffer. Two directions of movement of the signs of information units in the short-term memory – incoming and outgoing – are considered. Through the incoming direction, psychological mechanisms supply valuable signs of information units for parallel or sequential processing, integration into a holistic image and encoding, and through the outgoing – direct them to reproduction or to long-term memory for storage. In long-term memory, they activate the appropriate and inappropriate codes and represent their semantic concepts for both recognizing the signs of new information units and for reproducing memorized information in order to enrich, modify, consolidate or implement it.

Network on Chip Router Architecture Performance Analysis by using VHDL

on-Chip (NoCs) are increasingly used in many-core architectures. Todays technology for ASICs supports Networks-on-Chip designs which can have 100 million gates on a single chip. In order to implement a competitive NoC architecture in FP-GAs, the area occupied by the network should be kept to a minimum. This helps in utilizing maximum area by the logic while maintaining the performance of the router network. Reducing area also reduces the power consumption. NOC's designs promise to offer considerable advantages over the traditional bus-based designs, in solving the numerous technological, economic and productivity problems associated with billion-transistor system-on-chip development. Here, a very flexible network is designed to propose a highly scalable and can be easily changed to accommodate various needs. This proposed work focused on implementation, analysis and verification of a five port routers. The building blocks of the router are input/output, multiplexer/demultiplexer, crossbar switch, buffer register and arbiters. The arbiters uses the round robin algorithm. The proposed NOC architecture is simulated in Xilinx ISE10.1 software. The source code is written in VHDL. This design is suitable for building networks with irregular topologies and with low latency and high throughput. architecture are simple topology, extensibility and low area cost. This new approach employs explicit parallelism; exhibits modularity, therby need for global synchronization can be disappear. In a network-centric approach, the communication between IPs can take place in the form of packets. We suggest that a network-on-chip (NoC) resemble the interconnect architecture of high-performance parallel computing systems. The common characteristic of these kinds of architectures, is that the functional IP blocks communicate with each other with the help of intelligent switches.These switches can be considered as infrastructure IPs (I2Ps) (6) providing a robust data transfer medium for the functional IP modules. The proposed router is designed to be used in a reconfigurable computing platform.To minimize the area of an FPGA based device, the size of the router should be of small. Although there are a number of ASIC based router implementations, we restrict our discussion of the related work to FPGA-based

Algorithm and architecture design of the motion estimation for the H.265/HEVC 4K-UHD encoder

This paper presents the algorithm and the architecture of the high-throughput motion estimation system for the H.265/HEVC encoder. The design allows the processing of [email protected] videos at the clock frequency of 400 MHz. The architecture embeds two parallel processing paths for the integer-pel and the fractional-pel motion estimation. The paths share the same memories. Access conflicts are avoided by the use of dual-port modules and register buffers for reused samples. In each clock cycle, the integer-pel and the fractional-pel path can evaluate one and four motion vectors for an 8 × 8 luma block, respectively. A separate interpolator for chroma additionally increases the throughput. The integer-pel path supports test zone search for 8 × 8 prediction blocks. The motion estimation for larger blocks is performed by the utilization of results of the 8 × 8 search. The search for rectangular PUs is performed only at the fractional-pel level and reuses partial costs computed for square PUs. As a consequence, a significant amount of computation is saved. Synthesis results show that the design can operate at 200 and 400 MHz when implemented in FPGA Arria II and TSMC 90 nm, respectively. The implemented algorithm is verified in the HM16 software. If [email protected] videos are encoded with the low-delay configuration, BD-PSNR and BD-rate are equal to ?0.026 dB and 1.64 %, respectively.

Structural models of finite-state machines for their implementation on programmable logic devices and systems on chip

Digital systems based on programmable logic devices and systems on chip often use register buffers for the transmission of signals between functional units. In this paper, structural models of finite state machines (FSMs) that allow the use of input and output buffer triggers as memory elements of the finite state machine are considered. To this end, a new classification of structural models of finite state machines is proposed in which all finite state machines are divided into six classes A, B, C, D, E, and F. In the models C and D, output buffer triggers are used as memory elements; in the models E and F, input buffer triggers are used for this purpose. A definition of the set of internal states of FSMs in each class is given and synthesis methods for the FSMs of the classes C-F are proposed. The results of experiments showed that the use of FSM models of the classes C-F reduces the number of internal memory elements by 2.22% to 25.83% on the average and sometimes even by 100%.

The Asymmetrical Effects of Divided Attention on Encoding and Retrieval Processes: A Different View Based on an Interference with the Episodic Register

In this study, we evaluate the conceptualization of encoding and retrieval processes established in previous studies that used a divided attention (DA) paradigm. These studies indicated that there were considerable detrimental effects of DA at encoding on later memory performance, but only minimal effects, if any, on divided attention at retrieval. We suggest that this asymmetry in the effects of DA on memory can be due, at least partially, to a confound between the memory phase (encoding and retrieval) and the memory requirements of the task (memory “for” encoded information versus memory “at” test). To control for this confound, we tested memory for encoded information and for retrieved information by introducing a second test that assessed memory for the retrieved information from the first test. We report the results of four experiments that use measures of memory performance, retrieval latency, and performance on the concurrent task, all of which consistently show that DA at retrieval strongly disrupts later memory for the retrieved episode, similarly to the effects of DA at encoding. We suggest that these symmetrical disruptive effects of DA at encoding and retrieval on later retrieval reflect a disruption of an episodic buffer (EB) or episodic register component (ER), rather than a failure of encoding or retrieval operations per se.

Performance Evaluation of Optimized Mobile IP Protocol Vis-à-vis Bit Map Indexing Method

Mobile IP is such a protocol that provides the mobility support in the Internet. However, even with some proposed optimization techniques, there are still some drawbacks in regard to improve its performance. In this paper, a novel bit map indexing scheme has been represented to improve the performance. In this scheme, each mobile node can be shifting to a foreign network which is associated with the Register Buffer by using bit map indexing method. A sender sends packets to the receiver which is stored further in the Register Buffer so that it could reach to the destination. During handoff, a mobile node could decide whether to move its buffer and report the handoff to the home agent, or, simply report the handoff to the buffer. In this way, this scheme optimizes the burden on the home agent so that the total cost of message delivery and mobility management can be mitigated. To evaluate the performance of the proposed scheme, a performance model has been developed, considering two way models for mobile nodes along with a proposed iterative algorithm for deriving a minimal point where the minimum cost parameter has been achieved. The results show that the new scheme can enable Mobile IP route optimization with proper handoff extension, irrespective of number of packets received during each shift. General Terms Data Transfer and performance evaluation for Mobile IPv4 by novel Bit Map Indexing Method along with algorithm.

An Engineering Design of 4-bit Special Purpose Microprogrammed Processor

This work is a complementary part for what we proposed in [1]. In this paper, an undergraduate design experience for special purpose 4-bit microprocessor using the skills learned from digital logic design and Microprocessors courses is presented. The experience started in [1] by designing the ALU using the hardware printed circuit board and we are following it by completing the design by the instruction set architecture and the microprogram code. Our microprocessor contains – in addition to the ALU- six registers: A 4-bit accumulator register, Flag register that holds only zero (Z) and carry (C) flags, Program counter register (PC), Memory address register (MAR), Instruction register (IR), and Buffer Register. All programs and data are stored in the 1k RAM.

Digital phase meter

FIELD: radio engineering. SUBSTANCE: digital phase- meter is related to facilities measuring difference of initial phase signals in presence of variable phase component showing periodic character, specifically, in communication systems employing repeater incorporated in mix of equipment of artificial earth satellite staying in geostationary orbit. In correspondence with invention digital phasemeter includes two-channel converter of phase shift to time interval, 2AND/OR gate, first AND gate, counter, former, generator of quantizing pulses. Insertion of comparator, commutator, computer, time-setting unit, former of pulse of first measurement, buffer register, second AND gate, former of pulse of termination of second measurement, delay element, first OR gate, RS flip-flop, second OR gate, counter 19 of number of measurement cycles into phase-meter makes it feasible to exclude variable component caused by travel of satellite during measurement time, that is, to raise measurement accuracy of difference of initial phases. EFFECT: raised measurement accuracy of difference of initial phases. 1 dwg

An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories

This correspondence presents an optimal algorithm to detect any single "stuck-at-i," "stuck-at-O" fault and any combination of "stuck-at-I," "stuck-at-O" multiple faults in a random access memory using only the n-bit memory address register input and m-bit memory buffer register input and output lines. It is shown that this algorithm requires 4 X 2n memory accesses.

An Algorithm for Testing Random Access Memories

This correspondence presents an optimal algorithm to detect any single stuck-at-1 (s-a-1), stuck-at-0 (s-a-0) fault in a random access memory using only the n-bit memory address register input and m-bit memory buffer register input and output lines. It is shown that this algorithm requires 4 X 2nmemory accesses.

Design of queuing buffer register size

Design of queuing buffer register size

A Computer Interface for Efficient Zero-Crossing Interval Measurement

A technique is described which makes use of a hardware computer interface to efficiently extract zero-crossing interval information from continuous time signals. Each zero-crossing of the input waveform causes the contents of a clock register to be transferred into a clock buffer register simultaneously with the generation of a computer interrupt. Following this, the clock register is restarted and further zero-crossings are prohibited from affecting the device for a set length of time. This length of time is preset to disallow the interruption of the computer until the present zero-crossing interval can be processed. The interrupted computer may read the clock buffer register which represents the elapsed time between the previous two zero-crossings. Since this method results in the measurement of zero-crossing interval information with a minimum computer involvement, a given computer can spend a maximum amount of time processing zero-crossing interval data. An implementation of the technique for use with a PDP-8/L computer is discussed.

DIDO — A most versatile pattern-unit with fast discriminator inputs and CAMAC- /PERSEUS-output facilities

We describe a pattern-unit with fast descriminator inputs, strobed coincidence with resolving time of 5 ns, buffer register with standard CAMAC read-out or the very fast PERSEUS read-out. The circuit is built in a 4-fold CAMAC plug-in unit.

A six-channel PDP-8 interface for nerve impulse data

An interface operating on the I/O bus of the LINC-8 has been built which accepts up to six channels of nerve impulse data simultaneously at rates up to 4,000 pps/channel. By means of a 100-KHz clock and a 17-bit counter, the time of occurrence of each nerve impulse is strobed into one of six 17-bit buffer registers. The strobe causes a program interrupt to occur. Two I/O instructions are used to read the buffers into the PDP-8 accumulator. Additional instructions for skipping on data or overflow, enabling the counter, clearing the overflow flag, and clearing the counter are available.

The stacking register - a simultaneous input/output buffer

A simultaneous input/output buffer register, called the “stacking register” is described. Each word accepted by this register is stacked at its other end from where it can be transmitted to the acceptor. This can buffer data from a random source of information with instantaneous frequency higher than that of an acceptor but with average frequency equal or smaller than the average frequency of the acceptor. The logic of the stacking register and its control unit is given. The relation between the length of the stacking register and the input and output frequencies is derived.