Network on Chip Router Architecture Performance Analysis by using VHDL

Abstract

on-Chip (NoCs) are increasingly used in many-core architectures. Todays technology for ASICs supports Networks-on-Chip designs which can have 100 million gates on a single chip. In order to implement a competitive NoC architecture in FP-GAs, the area occupied by the network should be kept to a minimum. This helps in utilizing maximum area by the logic while maintaining the performance of the router network. Reducing area also reduces the power consumption. NOC's designs promise to offer considerable advantages over the traditional bus-based designs, in solving the numerous technological, economic and productivity problems associated with billion-transistor system-on-chip development. Here, a very flexible network is designed to propose a highly scalable and can be easily changed to accommodate various needs. This proposed work focused on implementation, analysis and verification of a five port routers. The building blocks of the router are input/output, multiplexer/demultiplexer, crossbar switch, buffer register and arbiters. The arbiters uses the round robin algorithm. The proposed NOC architecture is simulated in Xilinx ISE10.1 software. The source code is written in VHDL. This design is suitable for building networks with irregular topologies and with low latency and high throughput. architecture are simple topology, extensibility and low area cost. This new approach employs explicit parallelism; exhibits modularity, therby need for global synchronization can be disappear. In a network-centric approach, the communication between IPs can take place in the form of packets. We suggest that a network-on-chip (NoC) resemble the interconnect architecture of high-performance parallel computing systems. The common characteristic of these kinds of architectures, is that the functional IP blocks communicate with each other with the help of intelligent switches.These switches can be considered as infrastructure IPs (I2Ps) (6) providing a robust data transfer medium for the functional IP modules. The proposed router is designed to be used in a reconfigurable computing platform.To minimize the area of an FPGA based device, the size of the router should be of small. Although there are a number of ASIC based router implementations, we restrict our discussion of the related work to FPGA-based