Refresh Scheme Research Articles

A Hybrid Scheme Combining Duplications and LDPC Decoding to Reduce NAND Flash

Abstract With the development of NAND flash, the storage density has become larger and larger, but the reliability has become lower and lower. To address this problem, stronger error correction codes, low-density parity-check (LDPC) codes, are widely used in flash memory. However, the direct use of LDPC codes for error correction has a great impact on the read and write performance of SSDs. Given this, this paper proposes a new mentality that combines replica and LDPC decoding methods to improve the read performance of solid state drives (SSDs). Considering the characteristics of the quantization level of LDPC soft-decision decoding, this paper proposes the IDSD (LDPC soft-decision decoding and duplication method) and IDHSD (a method combining duplication and LDPC hybrid decoding)schemes. These schemes are mainly for hot data. When reading the data, the IDSD scheme needs to first judge whether it is soft-decision decoding. Then, according to the number of quantization levels recorded, it needs to select whether to use duplication or soft-decision decoding to correct the error data. The IDHSD scheme does not need to judge the soft-decision decoding but directly uses the duplication after the hard-decision decoding fails. Both schemes reduce the average response time to a certain extent and optimize the read performance of the SSD. The experimental results show that compared with the Native Scheme, the average response delay time of the IDSD scheme decreases by 5–30% and the IDHSD scheme slashes by 5–38%. Compared with the Traditional Refresh Scheme, the average response delay time of the IDSD scheme cuts down by 1–30% and the IDHSD scheme lowers by 1–29%.

Reduce Refresh Operations on 3-D TLC nand Flash System via Wordline (WL) Interference

As the storage density of 3-D NAND flash memory increases, reliability issues become a bottleneck. Among all reliability issues, decreased retention time is the dominant one. To extend the retention time, data refresh is a straightforward approach. However, refresh operations introduce redundant operations, which hurt the performance of the 3-D NAND flash system. With the observation that retention time can be extended by wordline (WL) interference, this letter first proposes to extend retention time with WL interference practically, and then presents a refresh scheme, which refreshes only one-third of pages in a block and postpones the refresh on the remaining two-thirds of pages with WI. The evaluation results show that the refresh operations are reduced by 40.7% at most. Compared with previous work, the read and write response times are decreased by 31.2% and 43.5%, respectively, with a 7-day refresh period.

Energy-Optimized Content Refreshing of Age-of-Information-Aware Edge Caches in IoT Systems

The Internet of Things (IoT) brings internet connectivity to everyday devices. These devices generate a large volume of information that needs to be transmitted to the nodes running the IoT applications, where they are processed and used to make some output decisions. On the one hand, the quality of these decisions is typically affected by the freshness of the received information, thus requesting frequent updates from the IoT devices. On the other hand, the severe energy, memory, processing, and communication constraints of IoT devices and networks pose limitations in the frequency of sensing and reporting. So, it is crucial to minimize the energy consumed by the device for sensing the environment and for transmitting the update messages, while taking into account the requirements for information freshness. Edge-caching can be effective in reducing the sensing and the transmission frequency; however, it requires a proper refreshing scheme to avoid staleness of information, as IoT applications need timeliness of status updates. Recently, the Age of Information (AoI) metric has been introduced: it is the time elapsed since the generation of the last received update, hence it can describe the timeliness of the IoT application’s knowledge of the process sampled by the IoT device. In this work, we propose a model-driven and AoI-aware optimization scheme for information caching at the network edge. To configure the cache parameters, we formulate an optimization problem that minimizes the energy consumption, considering both the sampling frequency and the average frequency of the requests sent to the device for refreshing the cache, while satisfying an AoI requirement expressed by the IoT application. We apply our caching scheme in an emulated IoT network, and we show that it minimizes the energy cost while satisfying the AoI requirement. We also compare the case in which the proposed caching scheme is implemented at the network edge against the case in which there is not a cache at the network edge. We show that the optimized cache can significantly lower the energy cost of devices that have a high transmission cost because it can reduce the number of transmissions. Moreover, the cache makes the system less sensitive to higher application-request rates, as the number of messages forwarded to the devices depends on the cache parameters.

An Approximate DRAM Design with an Adjustable Refresh Scheme for Low-power Deep Neural Networks

A DRAM device requires periodic refresh operations to preserve data integrity, which incurs significant power consumption. Slowing down the refresh rate can reduce the power consumption; however, it may cause a loss of data stored in a DRAM cell, which affects the correctness of computation. This paper proposes a new memory architecture for deep learning applications, which reduces the refresh power consumption while maintaining accuracy. Utilizing the error-tolerant property of deep learning applications, the proposed memory architecture avoids the accuracy drop caused by data loss by flexibly controlling the refresh operation for different bits, depending on their criticality. For data storage in deep learning applications, the approximate DRAM architecture reorganizes the data so that these data are mapped to different DRAM devices according to their bit significance. Critical bits are stored in more frequently refreshed devices while non-critical bits are stored in less frequently refreshed devices. Compared to the conventional DRAM, the proposed approximate DRAM requires only a separation of the chip select signal for each device in a DRAM rank and a minor change in the memory controller. Simulation results show that the refresh power consumption is reduced by 66.5 % with a negligible accuracy drop on state-of-the-art deep neural networks.

A survey of the retention of GPs following the induction and refresher scheme in London

ABSTRACT The NHS faces challenges in recruiting and retaining GPs. The NHS Long Term Plan aims to increase NHS staffing levels as one of its objectives. The Induction and Refresher (I&R) Scheme supports this aim by providing a safe induction or return to UK practice for GPs who are new to UK general practice or who have been away from it for 2 years or more. An evaluation of the I&R Scheme in London shows that 94% of all doctors who have been through the Scheme remain on the Medical Performers List with 82% of respondents continuing to work in UK general practice. The implication is that the Scheme is successful in its aim of retaining GPs in NHS practice. Additionally, most respondents found the Scheme to be of value, practically and emotionally in supporting their return to practice whether they were UK returners or if they were new to UK general practice.

Tail Latency Optimization for LDPC-Based High-Density and Low-Cost Flash Memory Devices

Flash memory has been developed with bit density improvement, technology scaling, and 3-D stacking. With this trend, its reliability has been significantly degraded. Error correction code (ECC), such as low-density parity code (LDPC), which has strong error correction capability, has been deployed to solve this problem. However, one of the critical issues of LDPC is that it would introduce a long decoding latency on devices with low reliability. In this case, tail latency would happen, which will significantly impact the quality of service. In this work, a set of smart refresh schemes is proposed to optimize the tail latency. The basic idea of the work is to refresh data when the accessed data have a long decoding latency. Two smart refresh schemes are proposed for this work. The first refresh scheme is designed to refresh data with a long access latency when they are accessed several times. The second refresh scheme is designed to periodically check data with an extremely long access latency and refresh them. To further optimize the refresh overhead caused by the above refresh schemes, a dual-ECC-based refresh scheme is proposed. Besides, a mathematical model for all proposed schemes is constructed to clarify the benefit of each scheme. The experimental results show that the proposed schemes can significantly improve the tail latency with acceptable overhead. What is more, the access performance is well maintained compared with the state-of-the-art work.

Row hammer avoidance analysis of DDR3 SDRAM

A DDR3 SDRAM test setup implemented on the Griffin III test system from HILEVEL Technologies is used to analyse the row hammer bug. Row hammer pattern experiments are compared to standard retention tests for different manufacturing technologies. The row hammer effect is depending on the number of stress activation cycles. The analysis is extended to an avoidance scheme with refreshes similar to the Target Row Refresh scheme for the DDR4 SDRAM technology.

A Management Scheme of Multi-Level Retention-Time Queues for Improving the Endurance of Flash-Memory Storage Devices

As flash memory technology has been scaled down to 1x nm and more bits can be stored in a cell, the storage density of flash memory has been significantly improved. However, these technical trends also severely hurt the programming speed and endurance of flash memory. The internal data retention time is the duration for which a flash cell can correctly hold data. By relaxing internal data retention time, both the page programming speed and the block endurance could be improved. However, the retention time of flash memory typically requires to last for several years according to the industrial standard. Thus a refreshment scheme is required to deal with the decreasing of retention time. In this article, we propose multi-level retention-time queues with a management scheme to meet the retention-time requirement for a reliable storage system. Observing that many data are overwritten in hours or days in real workloads, multiple retention-time queues could effectively separate data with different update frequencies. There are three challenge issues for a proper design: (1) Since access pattern might change from time to time, a technical issue is how to promote/demote data so that data could be maintained in the proper retention-time queue to minimize the refreshment overhead. (2) Another technical issue is how to refresh each retention-time queue in time to guarantee data integrity. (3) Since blocks resided in different retention-time queue would suffer from different level of wearing, the third technical issue is how to estimate wearing status of flash-memory blocks in an effective and efficient manner to achieve wear leveling. In our scheme, data allocator, multi-level refresh module, garbage collector, and wear leveler are introduced to deal with these technical issues. Based on our experimental results, not only endurance and performance but also energy consumption of the flash-memory storage system could be significantly improved by our scheme.

The reflecting team: a new approach to case discussion.

Case discussion is embedded within the culture of general practice. It is integral to the way we run routine practice meetings, where issues such as child safeguarding and significant event reviews are discussed. However, the inevitable time constraints we face can produce a culture that privileges efficiency and outcome over complexity, subtlety, and emotion in these discussions. There is also the very human desire to collude by problematising the patient or offering simplistic solutions rather than looking at the wider system. In the learning sets I facilitate for GPs on the Induction and Refresher Scheme, we have tried out a new approach when discussing cases — the reflecting team. The reflecting team is designed to be used by groups of practitioners, none of whom need any special training to participate. One person, the case presenter, brings a real, unresolved professional dilemma to the group. …

DR Refresh: Releasing DRAM Potential by Enabling Read Accesses Under Refresh

Emerging data analytic workloads such as graph processing, neural network and edge data preprocesing desire efficient memory read operations. Unfortunately, due to the necessity of dynamic refresh, modern DRAM systems have to stall access during refresh cycles. As DRAM device density continues to grow, refresh operations can be a crucial throughput bottleneck. To fully unleash memory access performance, we revisit conventional refresh mechanism and DRAM architecture. We propose DR refresh, a specific refresh mechanism that enable read and refresh operations to be done simultaneously. We devise DR DRAM, a specific memory hardware system that can efficiently deploy DR refresh. Unlike traditional refresh, DR explores device refresh that only refreshes a designated device at a time. Meanwhile, DR increases read efficiency by recovering the inaccessible data that resides on a device under refreshing. We also propose Hybrid Refresh Main Memory (HRMM) which can designate refresh schemes (DR or traditional refresh) in a specific memory space. We expect that our design can benefit many real-life tasks such as SPEC CPU2006, CNN, LLT and PageRank.

Voltage-controlled magnetic tunnel junctions with synthetic ferromagnet free layer sandwiched by asymmetric double MgO barriers

Memory and computing applications utilizing voltage-controlled magnetic random-access memory (MRAM) require perpendicular magnetic tunnel junctions (pMTJs) capable of high thermal stability and large write efficiency at advanced technology nodes. We first discuss the scaling requirements for voltage-controlled MRAM to replace various existing memory applications at an advanced CMOS technology node, including cell size, thermal stability, interfacial perpendicular magnetic anisotropy (PMA), and voltage-controlled magnetic anisotropy (VCMA). For replacing volatile memories including SRAM, eDRAM, and DRAM, we employ the retention relaxation technique along with a DRAM-style refresh scheme in the analysis. To enhance both PMA and VCMA at scaled nodes, we explore pMTJs with asymmetric double MgO barriers sandwiching a synthetic ferromagnet (SyF) free layer. In a thin MgO/SyF free layer/thick MgO/fixed layer MTJ stack, the SyF free layer is realized in various ways: single layer (X = Ta, W, Mo, Ir) and bilayers (X = Ta/W, Mo/Ir) of heavy metals insertions in CoFeB/X/CoFeB and Co2FeAl/X/Co2FeAl structures, and multiple insertions in [CoFeB/X]n/CoFeB structures for n = 1–4. A VCMA coefficient of 36 fJ (V m)−1 is achieved in a MgO/CoFeB/Ta/CoFeB/MgO-based MTJ which is comparable to that of the single MgO barrier MTJ. We find PMA enhancement, although with VCMA reduction for an increasing number n of [CoFeB/X]n repetitions. In addition, we demonstrate large TMR of 78%, large interfacial PMA of 1.45 mJ m−2, and VCMA of 65 fJ (V m)−1 in a MgO/Co2FeAl/W/Co2FeAl/MgO-based MTJ annealed above 400 °C.

Evaluation of the reflecting team as an educational intervention

ABSTRACTBackground: The reflecting team is a way of exploring clinical or educational dilemmas. A key difference from traditional case discussion is that the case presenter is not actively involved in the group discussion but instead listens to the ideas and thoughts generated, without contributing to the narrative. The origins of the reflecting team are in family therapy and there is little evidence on how successfully the technique can be transposed to clinical or educational practice.Aim: To evaluate the effectiveness of the reflecting team as an educational intervention.Design and setting: Interpretive action research involving 10 GPs who were either enrolled on the Induction and Refresher Scheme or who were members of a learning set of GP educators.Method: Interview data were audio-recorded, transcribed verbatim and thematic analysis was used to identify themes.Results: The reflecting team appeared to be an effective and acceptable intervention. Key features of the reflecting team included the opening up of new perspectives, feeling validated by peers, the need for ground rules and the perception of the reflecting team as a practical tool.Conclusions: The reflecting team is a new way of undertaking case discussion in GP education and seems to offer some advantages over traditional case discussion. It lends itself well to learning groups and it is possible that the idea might be transposed to clinical settings too.

Retention-Aware DRAM Auto-Refresh Scheme for Energy and Performance Efficiency

Dynamic random access memory (DRAM) circuits require periodic refresh operations to prevent data loss. As DRAM density increases, DRAM refresh overhead is even worse due to the increase of the refresh cycle time. However, because of few the cells in memory that have lower retention time, DRAM has to raise the refresh frequency to keep the data integrity, and hence produce unnecessary refreshes for the other normal cells, which results in a large refresh energy and performance delay of memory access. In this paper, we propose an integration scheme for DRAM refresh based on the retention-aware auto-refresh (RAAR) method and 2x granularity auto-refresh simultaneously. We also explain the corresponding modification need on memory controllers to support the proposed integration refresh scheme. With the given profile of weak cells distribution in memory banks, our integration scheme can choose the most appropriate refresh technique in each refresh time. Experimental results on different refresh cycle times show that the retention-aware refresh scheme can properly improve the system performance and have a great reduction in refresh energy. Especially when the number of weak cells increased due to the thermal effect of 3D-stacked architecture, our methodology still keeps the same performance and energy efficiency.

Candidate feedback on the Induction and Refresher (I&R) scheme-simulated surgery

ABSTRACTThe simulated surgery examination is one of the tripos of entry assessments for the Induction and Refresher (I&R) Scheme. It is used to assess the clinical and consulting skills of GPs prior to a period of supervised practice. The assessment involves observing candidates consulting with simulated patients played by role-players presenting standardised cases. Additionally, this assessment provides an ‘educational prescription’ for both passing and failing candidates as well as evidence of linguistic competency for overseas candidates.A feedback questionnaire is administered to candidates immediately after the examination, to seek their views and to evaluate their experience of the exam. Between July 2015 and July 2018, 401 candidates completed the examination and questionnaire. Quantitative and qualitative data has been collected and analysed with the findings reported in this paper. Overall candidates are satisfied with the examination, and regard it as a valid assessment of their GP consulting skills. However, there are still concerns regarding the I&R application process although there is evidence that there has been a trajectory of improvement over the past three years. Candidate feedback obtained has been used in an iterative manner to ensure quality control of the examination as well as for prompting improvements in the process.

Associative Memory for Image Recovery with a High‐Performance Memristor Array

AbstractAssociative memory is one of the significant characteristics of the biological brain. However, it has yet to be realized in a large memristor array due to the high requirements on the memristor device. In this work, the multilevel memristor cell is optimized by employing an electro‐thermal modulation layer. Memristor devices show both high resistance, cell‐to‐cell uniformity, and multilevel resistive switching behaviors with good reliability. A Hopfield neural network is experimentally demonstrated on a 1k memristor array that is capable of realizing the associative memory function for emotion image recovery. By using both asynchronous and synchronous refresh schemes, complete emotion images can be recalled from partial information.

Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with selective refresh

A recent large-scale study revealed that the uncorrectable bit error rates in data center solid-sate drives (SSDs) may fall far below the JEDEC standard recommendations. Here, a new refresh policy is proposed to improve the tolerated raw bit error rate (RBER) based on the observation that (a) a small ratio of SSD units may have a much higher RBER than the rest and (b) the RBER is dominated by the retention error rate. An approach is used to estimate the remaining retention time, i.e., the reliable data storage time, of flash memory pages. This estimation can be performed each time a memory page is read based on the number of detected retention errors and the elapsed time since data was programmed or refreshed. The fact that the estimated remaining retention time is smaller than a maximum time interval before the next page access is an indication that data needs to be refreshed. It is estimated that the tolerated retention RBER can be increased by up to 35× over a storage period of 3 years if the stored data are checked on a monthly basis and refreshed only if necessary. The proposed technique has the ability to adapt the average time between refresh operations to the actual RBER. Maximum refresh time reductions of about 12× are reported as compared to systematic refresh schemes.

A Gradual Refreshing Scheme for Improving Tool Utilization

Maintaining tool availability is the key to ensure machining quality. To evaluate tool availability so as to improve its utilization, the tool diagnosis models for tool-remaining-useful-life (RUL) estimation and tool-state classification are required. These models need sufficient samples to cover all the variations of tool coating and chip friction. However, in general, it is not easy to collect enough samples in the early stage. This issue will delay the readiness of the tool diagnosis models. The purpose of this letter is to propose a gradual refreshing scheme for modeling, running, and refreshing tool diagnosis models. In addition, a sample extension method is presented for reducing modeling time and enhancing accuracy of tool-state classification. The examples of engine-case machining are adopted in this letter to illustrate how the system works for estimating tool-RUL, classifying tool-states, and further, improving tool utilization.

Minimizing Retention Induced Refresh Through Exploiting Process Variation of Flash Memory

Refresh schemes have been the default approach in NAND flash memory to avoid data losses. The critical issue of the refresh schemes is that they introduce additional costs on lifetime and performance. Recent work proposed to minimize the refresh costs by using uniform refresh frequencies based on the number of program/erase (P/E) cycles. However, from our investigation, we find that the refresh costs still have a high burden on the lifetime performance. In this paper, a novel refresh minimization scheme is proposed by exploiting the process variation (PV) of flash memory. State-of-the-art flash memory always has significant PV, which introduces large variations on the retention time of flash blocks. In order to reduce the refresh costs, we first propose a new refresh frequency determination scheme by detecting the supported retention time of flash blocks. If the detected retention time is large, a low refresh frequency can be applied to minimize the refresh costs. Second, considering that the retention time requirements of data are varied with each others, we further propose a data hotness and refresh frequency matching scheme. The matching scheme is designed to allocate data to blocks with right higher supported retention time. Through simulation studies, the lifetime and performance are significantly improved compared with state-of-the-art refresh schemes.

Efficient Adaptive Intra Refresh Error Resilience for 3D Video Communication

3D video wireless communication is being repeatedly called upon to play a greater role in the quest for economic and political stability, peace and understanding in the world. However, excessive error propagation in compressed 3D video can dramatically decrease perceived quality of experience (QoE). Recent error control strategies suggested that using adaptive intra refresh (AIR) tool is a good candidate for fulfilling quality of service (QoS) requirements for 3D video transmission over wireless networks. We propose multi-view video AIR (MVV-AIR) based on H.264/advance video coding (AVC) to mitigate transmission error propagation in a two-way communication system. With the MVV-AIR, both high active macroblocks and channel bit error rate (BER)are computed to generate MVV-AIR refresh map. The generated map is used to periodically insert a cyclic intra-refresh line macroblock to suppress spatiotemporal error propagation. Experimental results show that MVV-AIR outperforms traditional refresh scheme in error prone transmission environment with improved objective and subjective visual quality.

Alleviating Memory Refresh Overhead via Data Compression for High Performance and Energy Efficiency

DRAM memory suffers from increasingly aggravating refresh penalty, which causes significant performance degradation and power consumption. As memory capacity increases, refresh penalty has become increasingly worse as more rows have to be refreshed. In this work, we propose an effective refresh approach called Compression-Aware Refresh (CAR) to efficiently mitigate refresh overheads. We apply a data compression technique to store data in a compressed format so that the resultant sparse banks need only be partially refreshed. Because of compression, data blocks which are originally distributed across all the constituent chips of a rank only need to be stored in a subset of those chips, leaving banks in the remaining chips not fully occupied. As a result, the memory controller can safely skip refreshing memory rows which contain no useful data without compromising data integrity. Such a compression-aware refresh scheme significantly reduces the refresh and thus improves overall memory performance and energy efficiency. To further take advantage of data compression, we adopt a rank subsetting technique to enable accesses to only those occupied chips for memory requests accessing compressed data blocks. Evaluations using benchmarks from SPEC CPU 2006 and the PARSEC 3.0 on recent DDR4 memory systems have shown that CAR achieves up to 1.66x performance improvement (11.7 percent on average) and up to 45.9 percent energy reduction (27.3 percent on average), and reduce memory traffic by up to 99.9 percent for zero cache lines intensive workloads with an average of 66.3 percent across all benchmarks.