Reference Voltage Research Articles

Research on Design Method and Application of Bandgap Voltage Reference

Abstract. With the progress and development of modern science and technology, more and more fields are inseparable from analog IC, and the demand for analog IC is increasing. From aerospace to mobile phones and televisions, analog IC are an indispensable part of these fields. In analog IC, one of the most common core components is a voltage reference that outputs a stable voltage that is not affected by temperature. However, the working environment of the voltage source will be different in different fields, so the design of voltage reference that meets the needs of their respective fields is one of the key research topics today, but there is still a lack of comparison and summary of the advantages and disadvantages of the different structures of the voltage reference used in different fields. Therefore, the research theme of this paper is to introduce the structure of voltage reference used in different fields, and compare and analyze the advantages and disadvantages of different structures, and discuss the development direction of future voltage reference on this basis.

Curvature-Compensated Bandgap Voltage Reference with Low Temperature Coefficient

Resistance errors in bandgap reference (BGR) circuits often cause deviations in design indicators, and it is true that utilizing various compensation techniques mitigates the impact of resistance errors. In this paper, an original BGR circuit with 180 nm BCD processing is presented, which uses an improved high-order compensation and curvature compensation. The proposed BGR contains four main blocks, including a start-up stage, a first-order temperature compensation stage, a high-order temperature compensation stage, and a curvature compensation stage. Meanwhile, a trimming resistor array structure is designed to revise the temperature coefficient (TC) deviation of the test output voltage from the theoretical design value. Through wafer-level laser trimming technology, the measurement results are achieved with very little difference from the theoretical design value. The proposed BGR provides a stable reference voltage at 1.25 V with a low TC and strong power supply rejection (PSR). Within temperatures ranging from −45 °C to 125 °C, the measured TC shows an optimal value at 4.2 ppm/°C and the measured PSR shows −100 dB.

Charge-coupled device readout by digital-correlated double sampling

Charge-coupled devices (CCDs) play crucial roles in astronomy owing to their widespread use in the optical band, offering high sensibility, low noise, high dynamic range, and high spatial resolution. Recent advancements in CCDs have focused on improving the sub-electron noise levels for particle detection and enhancing readout speeds through simulation studies. The main objective of this study is to replace the analog processing of CCD signals using the digital-correlated double sampling (DCDS) technique. DCDS allows post-acquisition noise correction through intermittent sampling of an internal reference voltage to provide compact and flexible performance. In this study, DCDS was evaluated using two digital processing systems, namely, a 2.5 mega-samples per second (MSPS) 24-bit analog-to-digital converter (ADC) board and a 250 MSPS 16-bit ADC field-programmable-gate-array( FPGA)-based buffer memory board. The readout noise value at 74 kpix/s (7.1 e) was a significant improvement over that obtained with analog processing (9.7 e). The DCDS implementation demonstrates optimal signal-to-noise ratio for a wide range of readout speeds. Parameters such as the sample positions per pixel, number of samples, and number of pixels were identified to be essential in achieving an accurate gain value. Finally, hardware implementation of the DCDS IP core algorithm on a Xilinx Zynq-7000 AP system-on-a-chip (SoC) showed a significant improvement in power dissipation (7.1 W) compared to the analog Monsoon correlated double sample (CDS) circuit (13.6 W). The DCDS IP core implementation also showed a background noise reduction of up to 34% compared to DCDS offline readout processing using a Python algorithm.

Efficient voltage control strategy: observability design for multistage DC–DC buck converter

This paper emphasizes the significance of implementing an effective control system to enhance the performance of a three-stage DC–DC buck converter (TDDC). Herein, we present the development of an observer controller (OC) for TDDC, where average modeling of the DC–DC converter was employed alongside an observer algorithm for the OC. The primary focus is on the adoption of an observation topology aimed at enhancing system responsiveness under various conditions, including variable input voltages, reference voltage changes, load fluctuations, integration with photovoltaics, and battery charging. This approach ensures improved stability and performance, addressing the dynamic challenges inherent in such systems. A comparative analysis was conducted on two distinct control topologies for the proposed TDDC system, namely proportional–integral (PI) and advanced OC. Simulink software was used to model and simulate the proposed system. The results demonstrate lower rising and settling times of the TDDC for the OC and PI implementations, respectively. Additionally, the system with the OC eliminates 20% of the overshoot, while the system with OC minimizes the output voltage oscillations from 13% to 2% compared to the PI system. The OC was integrated into the TDDC to enhance system stability and improve the control loops, particularly the third loop. These improvements make the TDDC with OC suitable for application to renewable energy systems, microgrids, telecommunication networks, and electric vehicles, where precise control and stability are essential.

Integral Sliding Mode‐Composite Nonlinear Feedback Control Strategy for Microgrid Inverter Systems

To enhance the dynamic performance and robustness of the voltage control system of islanded microgrid inverters, a new control strategy combining integral sliding mode (ISM) control and composite nonlinear feedback (CNF) control is proposed. In ISM control, firstly, a new reaching law is designed to improve movement quality in the reaching phase by improving the power term and introducing the inverse tangent function. Then, to improve disturbance observation accuracy, a variable gain extended state observer is designed by improving the regulation mechanism of the state variables according to deviation control. Using the idea of variable damping, linear and nonlinear feedback are combined into CNF control. Specifically, linear feedback provides a small damping ratio for faster system response, while nonlinear feedback increases the damping ratio to improve steady‐state performance. Simulation results show that the integral sliding mode‐composite nonlinear feedback (ISM‐CNF) control strategy cam balances convergence speed and chattering better and achieves higher steady‐state accuracy than conventional strategies. Moreover, ISM‐CNF control has better robustness to reference voltage variations and disturbances caused by sudden load changes. Therefore, the ISM‐CNF control strategy can accomplish voltage control of islanded microgrid inverters quickly and steadily, effectively suppressing system disturbances and enhancing stability and power quality. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.

Research and optimization of the gain characteristics of cascode amplifiers

Abstract. With the continuous development of IC technology, high-performance operational amplifiers are widely used in various circuit systems such as high-speed Analog-to-Digital Converters (ADCs), Digital-to-Analog Converters (DACs), switched capacitor filters, bandgap voltage reference sources, precision comparators. The amplifier has become the core unit circuit of analog IC and mixed-signal IC design, and its performance directly affects the overall performance of the circuit and system. The design of high-performance operational amplifiers has always been one of the hotspots in the research of analog IC design in order to meet the needs of various application fields. Cascode Amplifier is a classic structure widely used in high-frequency and high-gain electronic circuits. This project aims to study the gain characteristics of cascode amplifiers, explore the main factors affecting their gain, and propose methods to optimize the gain. Through theoretical analysis and simulation, the influence of different parameters on gain is verified. Then the optimization strategy is summarized to provide a reference for actual circuit design.

Design of Area-Optimized Low-power Voltage Reference Circuits using a Modified Particle Swarm Optimization

Design of Area-Optimized Low-power Voltage Reference Circuits using a Modified Particle Swarm Optimization

A Low-Power 5-Bit Two-Step Flash Analog-to-Digital Converter with Double-Tail Dynamic Comparator in 90 nm Digital CMOS

Low-power portable devices play a major role in IoT applications, where the analog-to-digital converters (ADCs) are very important components for the processing of analog signals. In this paper, a 5-bit two-step flash ADC with a low-power double-tail dynamic comparator (DTDC) using the control switching technique is presented. The most significant bit (MSB) in the proposed design is produced by only one low-power DTDC in the first stage, and the remaining bits are generated by the flash ADC in the second stage with the help of an auto-control circuit. A control circuit produced reference voltages with respect to the control input and mid-point voltage (Vk). The proposed design and simulations are carried out using 90 nm CMOS technology. The result shows that the peak differential non-linearity (DNL) and integral non-linearity (INL) are +0.60/−0.69 and +0.66/−0.40 LSB, respectively. The signal-to-noise and distortion ratio (SNDR) for an input signal having a frequency of 1.75 MHz is found to be 30.31 dB. The total power consumption of the proposed design is significantly reduced, which is 439.178 μW for a supply voltage of 1.2 V. The figure of merit (FOM) is about 0.054 pJ/conversion step at 250 MS/s. The present design provides low power consumption and occupies less area compared to the existing works.

ИЗМЕРЕНИЕ СОПРОТИВЛЕНИЯ ЛАКОКРАСОЧНОГО ПОКРЫТИЯ В ЭЛЕКТРОЛИТЕ

The use of known methods for measuring the electrical resistance of a protective coating in an electrolyte is associated with the danger of using high voltage, which accelerates degradation of the coating. The structural diagram of a measuring device operating at a low voltage of up to 1.5 V is substantiated. The device contains two galvanic cells with an electrolyte, a capacitor, a switch, a digital multimeter, and a three-position switch. One galvanic cell is attached to the coating on a carbon steel plate and is equipped with an electrode made of stainless steel. The second galvanic cell is equipped with electrodes made of carbon and stainless steel. It is a source of reference voltage. The input resistance of the multimeter from 1 MOhm serves as a reference resistance. The maximum value of the measured coating resistance reaches 1400 MOhm. A formula is obtained for calculating the specific electrical resistance of the paint and varnish coating in an electrolyte solution. Using the manufactured device, the dynamics of changes in the specific electrical resistance of two coatings made of Raptor polyurethane paint with a hardener are studied. The coatings were applied in two and three layers, the duration of testing in the borofoska solution was 200 days. Upon completion of the tests, the specific electrical resistance of the three-layer coating decreased from 480 to 20 MOhm∙m, it was 4 times greater than the two-layer coating. This result indicates a significant increase in the protective resistance of the polyurethane coating after applying the third layer.

Design of Voltage–Current Reference Source in CMOS Technology

A design methodology for a resistorless low-power two-in-one voltage and current reference source working in subthreshold and moderate regions is described. The presented novel universal reference voltage–current source was implemented in ten different designs for seven different CMOS technologies. Six versions of these designs were silicon-proven using four different CMOS technologies. The example of implementation in 130 nm technology provides a reference current of 5 µA and reference voltage of 800 mV at supply voltages ranging from 0.9 V to 2.0 V with a total current consumption of 15 µA. The proposed circuit occupies a 1200 µm2 chip area and achieves 280 and 118 ppm/°C for all process corners and temperature variation from −40 °C to 125 °C. The power supply rejection ratio of output IREF without any filtering capacitor at 100 Hz and 10 MHz is 128 dB and 100 dB, respectively. The equivalent output current noise in the bandwidth from 1 Hz to 10 MHz reaches 9.1 nARMS.

Performance analysis of DC-DC Buck converter with innovative multi-stage PIDn(1+PD) controller using GEO algorithm

Power electronic converters are widely used in various fields of electrical equipment. Due to their fast dynamics and non-linear nature, controlling them requires dealing with various complexities. Therefore, having a well-designed, high-speed, and robust controller is critical to ensure the effective operation of these devices. In a DC-DC converter, steady-state performance with minimum error and fast dynamic response relies on controller design. This paper presents the design of a multi-stage PID controller with an N-filter combined with a one plus proportional derivative (1+PD) controller. This controller illustrates fast tracking reference voltage; additionally, it shows incredible results when the DC-DC converter operates in different modes. The parameters of the proposed controller are effectively determined using the golden eagle optimization (GEO) algorithm. Furthermore, a comprehensive comparison between the proposed controller, proportional–integral–derivative (PID), and fractional order PID (FOPID) controllers, as well as different metaheuristic optimization methods in various conditions, has been conducted to demonstrate the effectiveness of the proposed controller. The behavior of the closed-loop system under different conditions has been thoroughly investigated. The superior time and frequency domain characteristics of the closed-loop system with the PIDn(1+PD) controller highlight its superiority over other controllers. The demonstrated enhancements in settling time, voltage regulation accuracy, and transient response emphasize the potential applicability of the proposed control strategy in real-world power electronics systems, particularly in scenarios requiring high efficiency, stability, and dynamic performance.

Analysis of Mueller–Muller Clock and Data Recovery Circuits with a Linearized Model

With the development of high-speed analog-to-digital converter (ADC)-based wireline receivers, the Mueller–Muller clock and data recovery (MM-CDR) circuit has garnered increasing attention. But in the design stage, evaluating the loop performance of MM-CDR circuits in ADC-based wireline receivers is challenging due to the absence of a linearized model for a Mueller–Muller phase detector (MMPD). In this paper, a linearized model of the MMPD is proposed by analyzing the output probability of the MMPD in different transition patterns with random jitter injection, and the model is combined with an entire MM-CDR system to analyze the performance of the MM-CDR loop. Analysis of the linearized model and corresponding simulations indicate that when the reference voltage level in the MMPD is set equal to the amplitude of the average crossing voltage at the intersection of 011 and 110 patterns, the MMPD can obtain the maximum gain, which is determined by jitter, and the jitter transfer function and jitter tolerance can achieve optimum performance.

Modeling and Simulation of Wide-Frequency Characteristics of Electromagnetic Standard Voltage Transformer

To achieve the broadband applicability of standard voltage transformers in “dual high” power systems, an equivalent circuit model of the standard voltage transformer is first established. Using the complex magnetic permeability method and utilizing existing core parameters, the excitation impedance values are obtained. Next, based on the equivalent circuit model, the no-load error function of the standard voltage transformer is analyzed, and through simulation, the no-load error response curve of the standard voltage transformer in the frequency range of 20 Hz to 3000 Hz is derived. The simulation results indicate that within the 20 Hz to 700 Hz range, both the no-load ratio error and the no-load angular error meet the accuracy requirements, with the ratio error within ±0.05% and the angular error within 2′. Additionally, the derivation of the error transfer function demonstrates the correlation between the no-load error values and the number of turns and cross-sectional area of the standard voltage transformer. Simulation results, obtained by increasing and decreasing the number of turns and cross-sectional area by 10%, provide valuable insights for the error compensation and structural design of standard voltage transformers.

Intelligent Robust Controllers Applied to an Auxiliary Energy System for Electric Vehicles

This paper presents two intelligent robust control strategies applied to manage the dynamics of a DC-DC bidirectional buck–boost converter, which is used in conjunction with a supercapacitor as an auxiliary energy system (AES) for regenerative braking in electric vehicles. The Neural Inverse Optimal Controller (NIOC) and the Neural Sliding Mode Controller (NSMC) utilize identifiers based on Recurrent High-Order Neural Networks (RHONNs) trained with the Extended Kalman Filter (EKF) to track voltage and current references from the converter circuit. Additionally, a driving cycle test tailored specifically for typical urban driving in electric vehicles (EVs) is implemented to validate the efficacy of the proposed controller and energy improvement strategy. The proposed NSMC and NIOC are compared with a PI controller; furthermore, an induction motor and its corresponding three-phase inverter are incorporated into the EV control scheme which is implemented in Matlab/Simulink using the “Simscape Electrical” toolbox. The Mean Squared Error (MSE) is computed to validate the performance of the neural controllers. Additionally, the improvement in the State of Charge (SOC) for an electric vehicle battery through the control of buck–boost converter dynamics is addressed. Finally, several robustness tests against parameter changes in the converter are conducted, along with their corresponding performance indices.

A Sub-1 ppm/°C Reference Voltage Source with a Wide Input Range

With the continuous advancement of electronic technology, the application of high-voltage integrated circuits is becoming increasingly prevalent in fields such as power systems, medical devices, and industrial automation. The reference circuit within high-voltage integrated circuits must not only exhibit insensitivity to temperature variations but also maintain stability across a broad voltage supply. This paper presents a bandgap reference (BGR) source capable of operating over a wide input range. This BGR employs a high-order curvature compensation method to eliminate nonlinear voltage terms, resulting in minimal temperature drift. The circuit achieves an impressive temperature coefficient (TC) of 0.88 ppm/°C over a temperature range from −40 °C to 130 °C. To ensure stable operation within a 4–40 V range, the design incorporates a pre-regulation circuit that stabilizes the supply voltage of the BGR core at a fixed value, thereby enhancing the ability to withstand variations in power supply voltage.

Capacitor Voltage Feedback Active Damping With Reduced Computation Delay for Improving Voltage Control Performance of LC‐Type Grid‐Forming Inverter

ABSTRACTIn low‐voltage applications using low‐Q LC filters, alias‐free capacitor voltage acquisition can be achieved, but synchronous capacitor voltage sampling under high‐Q filters used in high‐voltage applications in grid‐forming converters causes some degree of distortion and results in degradation of the power supply quality. And the inherent 1.5 sampling periods that delay in this approach limit the control bandwidth, reduce the stability region, and result in an inadequate time domain response. Despite these shortcomings, this approach is widely accepted in practice. The conclusion of this paper is that shifting the capacitor voltage sampling instant to 2 µs before the pulse width modulation (PWM) reference voltage update results in almost the same distortion as synchronous sampling. However, it can improve the dynamic performance of the system. A distortion‐acceptable univariate feedback voltage dual‐loop active damping control topology with much reduced computational delay is proposed, which is based on an internal active damping loop using a discrete lead compensator and a proportional resonance controller in the external voltage loop.

An Ultra-Low Power, Low Voltage, Low Line Sensitivity, High PSRR, Voltage Reference for IoT Applications

An Ultra-Low Power, Low Voltage, Low Line Sensitivity, High PSRR, Voltage Reference for IoT Applications

Artificial neural network based decentralized current-sharing control for parallel connected DC-DC converters in DC microgrid application

To create a non-interrupted, economical and reliable direct current (DC) microgrid, multiple DC-DC converters can be connected in parallel. Current sharing among these multiple converters becomes essential for proper operation of the system. This study proposes an artificial neural network (ANN) based control technique for parallel connected DC-DC boost converters which ensures accurate current sharing according to the specified maximum limits. Levenberg-Marquardt algorithm-based ANN network is used to reduce the training time and, also to achieve near ≈ 100 % accuracy of the training data. ANN control provides better voltage regulation, accurate current sharing unlike the conventional proportional-integral (PI) based control which faces issues such as inaccurate current sharing, high transient, peak overshoots and steady state error during sudden change in the system. The efficient functioning of the proposed control method is verified by simulating two parallel connected DC-DC converters using MATLAB/Simulink. A hardware prototype of converters rating ≈ 250 W using TMS320F28379D Digital signal processor controller is also developed to verify the performance and effectiveness of the ANN based control in comparison to PI based technique. The ANN based technique is faster to achieve the reference voltage, and the peak overshoot is approximately 75 % lesser than the PI based control.

A simple picowatt 7.6 ppm/°C, 0.029 %/V line sensitivity fully-CMOS voltage reference with DIBL cancelation

In this paper, a 4-transistor sub-one-volt voltage reference with picowatt power consumption is presented. To achieve ultra-low power consumption and low-voltage operation, all transistors are designed to operate in subthreshold region. By proper design of the circuit, DIBL effect is also compensated to enhance temperature coefficient of the circuit and line sensitivity. The proposed circuit consists of only four different transistors (i.e. thick oxide, native VTH, medium VTH) in a self-biased scheme such that eliminates the need for any start-up circuit. A prototype of the proposed circuit that generates a 341-mV voltage reference is designed and simulated in a standard 0.18-µm CMOS technology. The proposed reference circuit exhibits an average temperature coefficient of 7.6 ppm/°C across all process corners while the total power consumption is as low as 249 picowatt. The average line sensitivity of the circuit is 0.029 %/V within a wide supply range of 0.6 to 3.3 V. Ultra-low power consumption and line sensitivity, and excellent thermal stability render it ideal for integration into RFID and IoT applications.

Demonstration of dual Shapiro steps in small Josephson junctions.

Bloch oscillations in small Josephson junctions were predicted theoretically as the quantum dual to Josephson oscillations. A significant consequence of this prediction is the emergence of quantized current steps, so-called dual Shapiro steps, when synchronizing Bloch oscillations to an external microwave signal. These steps potentially enable a fundamental standard of current I, defined via the frequency f of the external signal and the elementary charge e, I=±n×2ef, where n is a natural number. Here, we realize this fundamental relation by synchronizing the Bloch oscillations in small Al/AlOx/Al Josephson junctions to sinusoidal drives with frequencies from 1 to 6 GHz and observe dual Shapiro steps up to I≈3 nA. Inspired by today's voltage standards and to further confirm the duality relation, we investigate a pulsed drive regime and observe an asymmetric pattern of dual Shapiro steps. This work confirms quantum duality effects in Josephson junctions and paves the way towards a range of applications in quantum metrology based on well-established fabrication techniques and straightforward circuit design.