Referenceless Clock And Data Recovery Research Articles

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a triple-inductive transimpedance amplifier (TIA), direct current (DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers (VGA), and a reference-less clock and data recovery (CDR) circuit with built-in equalization technique. The TIA/VGA front-end measurement results demonstrate 72-dBΩ transimpedance gain, 20.4-GHz −3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10−12 BER at 26 Gb/s for a 215−1 PRBS input with a −7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.

A Wide-Range FD for Referenceless Baud-Rate CDR Circuits

A wide-range frequency detector (FD) is presented for baud-rate clock and data recovery (CDR) circuits. It achieves a wide frequency capture range, a short lock time, and a low power. By using this FD, a referenceless quarter-rate CDR circuit with a one-tap decision feedback equalizer is fabricated in 40-nm CMOS technology. The active area of this CDR circuit is 0.0999mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and its power is 44mW while the data rate is 16.8Gbps. The calculated energy efficiency of this CDR circuit is 2.62pJ/b.

A Fully Digital Semirotational Frequency Detection Algorithm for Bang–Bang CDRs

This brief presents a new frequency acquisition method using a semirotational frequency detection (SRFD) algorithm for referenceless clock and data recovery (CDR) in a serial-link receiver. The proposed SRFD algorithm classifies the bang–bang phase detector (BBPD) outputs to estimate the current phase state and detects the frequency mismatch between the input data and the sampling clock. The voltage-controlled oscillator (VCO)-track path in a digital loop filter (DLF) enables online calibration of a drifted frequency of the VCO caused by temperature or voltage variation after a frequency acquisition. The proposed algorithm can be implemented as a digitally synthesized circuit, lowering design efforts for referenceless CDRs. A 10-Gb/s transceiver IC with the proposed algorithm, fabricated in a 65-nm CMOS process, demonstrates successful recovery of the input phase without any reference clock.

A low-power reference-less clock/data recovery for visible light communication devices requiring low data throughput

In this study a reference-less clock and data recovery (CDR) is designed and developed for the low speed visible light communication system based Internet of Things (IoT) tags. Design system incorporates an off-chip photodiode and an integrated-on chip front-end receiver with the reference-less CDR. For an IoT tags low power consumption, low supply voltage, and small area are the major design constraint. Considering these constraints, the circuit of the front-end receiver incorporate the near-threshold cascode current mirror based transimpedance amplifier, low pass filter and a comparator. On the other-hand, low power all-digital phase locked loop-based reference-less CDR is design herein with a modified loop filter, auto tune digital control oscillator and auto duty cycle adjustment circuit. The circuit is implemented in an integrated chip with area of 0.728 mm2 via TSMC 180 nm process. Experimental measurement results of the tapeout chip shows that the phase noises are − 39.54 dBc/Hz @ 1 kHz, − 80.35 dBc/Hz @ 10 kHz and − 92.26 dBc/Hz @ 100 kHz. The measured jitter in the recovered clock is 3.312 ns (0.0033 UI). At 1 Mbps, the measured total power consumption is 5.58 μW. The achieve results shows that the implemented circuit in this study highly support the commercial low data rate based optical wireless sensing nodes for IoT tags.

8–10 Gbit/s full synthesised continuous‐half‐rate reference‐less all‐digital CDR with sub‐harmonic frequency extraction

Continuous-rate all-digital reference-less clock and data recovery (CDR) circuit that utilises a sub-harmonic extraction scheme for wide-range frequency detection is presented. In the proposed CDR, the capture range of the frequency locked loop (FLL) is extended to the tuning range of digital controlled oscillator, thanks to the subharmonic extraction scheme. The frequency errors of FLL in lock state are within the tracking range of CDR loop. The prototype reference-less all-digital CDR, fabricated using a 40 nm CMOS technology, successfully detects 8–10 Gbit/s PRBS 231 − 1 data and produces the recovered clock. The CDR consumes 29 mW from a supply voltage of 1 V for 10 Gbit/s input data. The measured RMS jitter of the recovered clock is 2.24 ps.

A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS

This paper presents a referenceless baud-rate clock and data recovery (CDR) incorporated with a continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer (DFE) to achieve data rates from 22.5 to 32 Gb/s across a channel with Nyquist loss ranging from 10.1 to 14.8 dB. The referenceless CDR includes a proposed frequency acquisition scheme that consists of two parts: frequency detection and frequency correction. Frequency detection is achieved by examining rising and falling data waveforms to detect discrepancies between the data rate and the locally recovered clock frequency. Frequency correction uses digitally adjustable asymmetry of the proposed adjustable baud-rate phase detector to correct any frequency error. The receiver is implemented in the TSMC 28-nm CMOS process with an analog front end consisting of a CTLE, sampling comparators, a digitally controlled oscillator, and a digital back end consisting of synthesized digital CDR logic. The open-loop frequency detector range is measured to be 39%. The closed-loop CDR capture range is measured to be 34%, limited by test equipment. The proposed frequency acquisition scheme improves the measured CDR capture range by up to 227×. At 32 Gb/s, the entire receiver consumes 102.04 mW, achieving energy consumption below 3.19 pJ/b.

On Frequency Detection Capability of Full-Rate Linear and Binary Phase Detectors

Until now, it has been known that the full-rate linear and binary phase detectors (PDs) cannot detect the frequency difference between the received data and the recovered clock in clock and data recovery (CDR) loops. In this brief, we study the frequency characteristics of the full-rate linear and binary PDs and show that, unlike the binary PD, the linear PD has not only phase detection capability but also frequency detection capability intrinsically. According to our frequency-locked loop analysis, the locking trajectory of a referenceless CDR with only the full-rate linear PD in the single-loop architecture can be represented by using an exponential decay function with a single time constant. MATLAB Simulink simulations agree well with the predicted locking trajectory, which verifies that the full-rate linear PD has frequency detection capability.

A &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$4\times 5$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-Gb/s 1.12-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu \text{s}$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels

A $4\times 5$ -Gb/s reference-less receiver is proposed in a 0.13- $\mu \text{m}$ CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded from the main channel to the subchannels, and skews between the channels are compensated by a skew compensation algorithm. In the main channel, the reference-less CDR achieves a 1.12- $\mu \text{s}$ locking time, and the measured standard deviation of VCO gain is reduced from 0.33 to 0.08. The recovered clock jitter in the main channel is 1.591 ${\rm ps}_{{\mathrm{rms}}}$ , and the power consumption of the main channel and the subchannels are 3.53 and 2.16 mW/Gb/s, respectively.

A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization

This paper presents a continuous-rate reference-less clock and data recovery (CDR) circuit with an asynchronous baud-rate sampling to achieve an adaptive equalization as well as a data rate acquisition. The proposed scheme also enables the use of a successive approximation register (SAR) based approach in the frequency acquisition and results in a fast coarse lock process. The CDR guarantees a robust operation of a fine locking even in the presence of large input data jitter due to the adaptive equalization and a jitter-tolerable rotation frequency detector (RFD) that eliminates a dead-zone problem with a simple circuitry. The fabricated CDR in 65 nm CMOS shows a wide lock range of 0.65-to-10.5 Gb/s at a bit error rate (BER) of $10^{-12}$ . The CDR consumes 26 mW from a single supply voltage of 1 V at 10 Gb/s including the power consumption for equalizer. By an adaptive current bias control, the power consumption is also linearly scaled down with the data rate, exhibiting a slope of about 2 mW decrease per Gb/s.

An 8–11 Gb/s Reference-Less Bang-Bang CDR Enabled by “Phase Reset”

This paper embeds a “phase-reset” scheme into a bang-bang clock and data recovery (CDR) to periodically realign the clock phase to the data rising edge using a gated-VCO. This reduces both the CDR lock time and bit errors during pull-in, while increasing the CDR capture range. The CDR is fabricated in 65-nm CMOS, operates at 8-11 Gb/s, and demonstrates a 9 × increase in capture range. The CDR consumes 84 mW during lock, and 48 mW in steady state.

0.6–2.7-Gb/s Referenceless Parallel CDR With a Stochastic Dispersion-Tolerant Frequency Acquisition Technique

A 0.6-2.7-Gb/s phase-rotator-based four-channel digital clock and data recovery (CDR) IC featuring a low-power dispersion-tolerant referenceless frequency acquisition technique is presented. A quasi-periodic reference clock signal extracted directly from a dispersed input signal is distributed to digitally controlled phase rotators in the CDR ICs for phase acquisition. A multiphase frequency acquisition scheme is employed for the reduction of the clock jitter. The measurement results show that the proposed design offers a lower frequency offset and clock noise floor under channel dispersion, as compared with conventional designs. The proposed four-channel digital CDR IC is fabricated in a 90-nm CMOS process. The figure of merit for a single channel is 8 mW/Gb/s such as a feedforward equalizer, a decision-feedback equalizer, and a referenceless CDR.

A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

Clock and data recovery (CDR) circuits with wide frequency acquisition range offer flexibility in optical communication networks, help reduce link power through activity-based rate adaptation, and minimize cost with a single-chip multi-standard solution. Extracting the bit rate from the incoming random data stream is the main challenge in implementing reference-less CDRs. A conventional rotational frequency detector has a limited acquisition range of about ±50% of the VCO frequency, consumes large power, and is susceptible to harmonic locking. Extending its range requires additional high-speed circuitry and a complex state machine [1]. The DLL-based architecture in [2] requires passing high-speed data through a long string of power-hungry buffers, imposes stringent matching requirements, and works only with ring oscillators. Other approaches require detailed statistical [3] or timing analysis [4]. Further, all the above techniques are only suitable for full-rate CDRs. In this paper, we present a reference-less half-rate CDR that uses a sub-harmonic extraction method to achieve unlimited frequency acquisition range. This technique is capable of locking the CDR to within 40ppm of any sub-rate of the data (making it applicable for any sub-rate CDR architecture), while being immune to undesirable harmonic locking. This CDR also integrates a calibration loop to improve robustness to input duty cycle error.