Reference Clock Jitter Research Articles

A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance

Ring oscillator (RO)-based frequency synthesizers have been widely used in Systems on Chip (SoCs) due to their tiny active area and broad tuning range. However, they also experience significant spur and jitter. Based on an extensive evaluation of the factors of space, power usage, reference clock frequency, jitter, and reference spur. In order to achieve low jitter and low spurious, we present a time-to-voltage conversion phase-locked loop (TVC-PLL) based on a RO in this study. To achieve a wide range of adjustable phase-detection gain, we introduce a time-to-voltage converter (TVC-PD) as a phase detector. We suggest a pre-phase locked module based on orthogonal output clocks help with locking in order to address the problem of the limited phase detection range of conventional TVCs, which can only be used for frequency-locked loops (FLLs). According to simulation results, our suggested TVC-PLL is built using TSMC 65-nm CMOS, uses 4.053 mW of power, and occupies an active area of 0.024 mm2 at a working frequency of 2.4 GHz. It achieves an RMS jitter of 625.4 fs in the 10k to 100MHz frequency range, a reference spur of −77.7 dBc, and a figure-of-merit (FoMJ) of −238.0 dB.

A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS Technology

A phase-locked loop (PLL) for analog video RGB signal acquisition interface requires precise clock generation from a very noisy and low-frequency horizontal synchronization signal (HSYNC). In such applications, the frequency multiplication ratio is always larger than 800 and can be up to over 2600. The output pixel clock has to be phase aligned to the HSYNC. Otherwise, the displayed image will become blurry. A fast phase tracking all-digital PLL (ADPLL) for video pixel clock generation in a 65 nm CMOS technology is presented in this paper. In the proposed ADPLL, the digital loop filter eliminates the reference clock jitter effects and then the period jitter of the output pixel clock can be reduced. A time-to-digital converter (TDC) and a delta-sigma modulator (DSM) are used to perform the fast phase tracking, and the tracking jitter is controlled at less than one-third of the output pixel clock period. As compared to prior studies, the proposed ADPLL does not require an extra external oscillator to overcome the reference clock jitter effects. Thus, it has a small chip area and low power consumption, and is well-suited to video pixel clock generation applications in 65 nm CMOS process.

Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter

Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear systems due to the binary phase detector (BPD). While they are typically used for clock and data recovery, the ongoing trend toward digital loop implementations has resulted in several digital BBPLLs (DBBPLLs) suitable for frequency synthesis. This brief investigates the effect of nonaccumulative reference clock jitter (due to white phase noise) in second-order DBBPLLs, comparing the output jitter with that of first-order DBBPLLs. For small clock jitter, the nonlinear loop behavior is modeled as a 2-D Markov chain, and the output jitter is smaller than but close to that of a first-order loop. For large clock jitter, the BPD nonlinearity is linearized, and the output jitter is larger than that of a first-order loop; it is proportional to the clock jitter and inversely proportional to the square root of the stability factor-the ratio of the proportional-path gain to the integral-path gain of the digital loop filter.

Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter

Bang-bang phase-locked loops are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). In the presence of jitter, the nonlinear loop is typically analyzed by linearizing the BPD and applying linear transfer functions in the analysis. In contrast to a linear phase detector, the linearized gain of a BPD depends on the rms jitter and the type of jitter (either nonaccumulative or accumulative). Previous works considered the case of nonaccumulative reference clock jitter and showed that the BPD gain is inversely proportional to the rms jitter when the latter is small or large. In this brief, we consider the case of accumulative digitally-controlled oscillator (DCO) jitter and derive an asymptotic closed-form expression for the BPD gain, which becomes exact in the limit of small and large jitter. Contrary to the reference clock jitter case, the BPD gain is constant for small DCO jitter and is inversely proportional to the square of jitter for large DCO jitter; in the latter case, the timing jitter has a normal Laplace distribution.

Effect of Reference Clock Jitter and Demonstration of Near Image-Free Operation for the ADPLL

The effect of reference clock jitter on the all-digital phase-locked loop (ADPLL) is considered. The analog-to-digital interface [e.g., a time-to-digital converter (TDC)] is considered only briefly. For the digital-to-analog interface [e.g., a digitally controlled oscillator (DCO)], the analysis is studied in detail. The power spectral density and the integrated power of the ADPLL's output phase noise are assessed for two types of reference clock jitter: 1) small correlated jitter (such as for a typical reference oscillator) and 2) uncorrelated jitter. Uncorrelated clock jitter (intentionally added at the DCO), which is uniformly spread over a sampling interval, is shown to nearly remove the digital images at the ADPLL output, which significantly lowers the minimum reference clock frequency in wireless designs.

A second-order semidigital clock recovery circuit based on injection locking

A compact (1 mm × 160 μm) and low-power (80-mW) 0.18-μm CMOS 3.125-Gb/s clock and data recovery circuit is described. The circuit utilizes injection locking to filter out high-frequency reference clock jitter and multiplying delay-locked loop duty-cycle distortions. The injection-locked slave oscillator output can have its output clocks interpolated by current steering the injecting clocks. A second-order clock and data recovery is introduced to perform the interpolation and is capable of tracking frequency offsets while exhibiting low phase wander.

Performance of digital collective antenna systems in the presence of phase noise and clock jitter

SMATV (satellite master antenna television) systems can be considered as an optimal distribution network for a fast and effective introduction of digital TV to the end users in several European countries and is an alternative in those which can be used countries their that are developing infrastructures. This paper studies the performance of digital collective systems in the presence of a noisy phase reference (phase noise) and a noisy clock reference (clock jitter). For this purpose, an attempt has been made to characterize the performance of this digital transmission system through the bit error rate (BER) or symbol error rate (SER) as a function of the Eb/No ratio. The Eb/No ratio has been parametrised by phase noise and clock jitter, obtained through computer simulations. It is shown that these effects produce a significant increase in the BER/SER performance. The simulator used was the SPW (Signal Processing WorkSystem) by means of which the BER/SER has been estimated using a quasianalytical (semianalytic) approach and the Monte Carlo method, so that the results can be compared and checked.