Reed-Solomon Decoder Research Articles

Understanding binary-Goppa decoding

This paper reviews, from bottom to top, a polynomial-time algorithm to correct t errors in classical binary Goppa codes defined by squarefree degree- t polynomials. The proof is factored through a proof of a simple Reed–Solomon decoder, and the algorithm is simpler than Patterson's algorithm. All algorithm layers are expressed as Sage scripts backed by test scripts. All theorems are formally verified. The paper also covers the use of decoding inside the Classic McEliece cryptosystem, including reliable recognition of valid inputs.

Single trace HQC shared key recovery with SASCA

This paper presents practicable single trace attacks against the Hamming Quasi-Cyclic (HQC) Key Encapsulation Mechanism. These attacks are the first Soft Analytical Side-Channel Attacks (SASCA) against code-based cryptography. We mount SASCA based on Belief Propagation (BP) on several steps of HQC’s decapsulation process. Firstly, we target the Reed-Solomon (RS) decoder involved in the HQC publicly known code. We perform simulated attacks under Hamming weight leakage model, and reach excellent accuracies (superior to 0.9) up to a high noise level (σ = 3), thanks to a re-decoding strategy. In a real case attack scenario, on a STM32F407, this attack leads to a perfect success rate. Secondly, we conduct an analogous attack against the RS encoder used during the re-encryption step required by the Fujisaki-Okamoto-like transform. Both in simulation and practical instances, results are satisfactory and this attack represents a threat to the security of HQC. Finally, we analyze the strength of countermeasures based on masking and shuffling strategies. In line with previous SASCA literature targeting Kyber, we show that masking HQC is a limited countermeasure against BP attacks, as well as shuffling countermeasures adapted from Kyber. We evaluate the “full shuffling” strategy which thwarts our attack by introducing sufficient combinatorial complexity. Eventually, we highlight the difficulty of protecting the current RS encoder with a shuffling strategy. A possible countermeasure would be to consider another encoding algorithm for the scheme to support a full shuffling. Since the encoding subroutine is only a small part of the implementation, it would come at a small cost.

The hybrid method for finding the roots of a polynomial over finite fields based on affine expansion

This paper proposes a hybrid method to find the roots of a polynomial in a finite field based on combining the polynomial decomposition into the sum of multiples of the affine polynomial with the analytical method to find the roots of low-order polynomials. The proposed method allows a significant reduction in complexity and is applicable in the design of low-latency BCH and Reed-Solomon decoders.

Symbol-level iterative information set decoding of RS codes

This paper presents the implementation of a low-complex iterative symbol-level decoding scheme for Reed-Solomon codes. Most soft-decision iterative decoders for Reed-Solomon codes work on a bit level due to the efficient passing of soft information due to the sparsity of the binary parity check matrix. These decoders yield a good error correction performance, but this comes at the cost of an increased computational complexity resulting from working at a bit-level. This study aims to lower the computational complexity of iterative decoding of Reed-Solomon codes by introducing a high-performance soft-decision iterative Reed-Solomon decoder that works on a symbol-level, in contrast to the bit-level implementation used in most iterative Reed-Solomon decoders. The proposed algorithm utilises soft information to decode while applying information set decoding techniques to an extended parity check matrix. The use of the extended parity check matrix provides additional parity check equations which assist the algorithm in determining the correct information set of symbols used in the decoding process. For a given (n,k) Reed-Solomon code, the algorithm converges to a valid codeword by correctly decoding a specified information set of k symbols from the received vector. Simulations run show the proposed algorithm performs favourably when compared to other symbol-level iterative decoders while working at a relatively lower complexity.

Development and Validation of an optimized syndromes block for reed solomon decoder

Reed Solomon decoder plays an indispensable role in many applications involving data transmission, storage applications and Video broadcasting DVB-T and DVB-S2. In this work we propose a new optimized parallel syndrome block [67] for the Reed Solomon RS code (15,11) used in digital Video broadcasting DVB-T. Therefore, this proposed parallel block is compared to the serial syndrome block existing. On the basis of this technique a new architecture based on three syndromes in parallel is developed. This technique reduces both the energy consumption and the number of iterations. The RS code (15, 11) is composed of 255 symbols that are multiples of 3. The symbols are entered in parallel in the syndrome block. These decoding algorithms developed in this work are compared with the existing algorithms, and they are evaluated through a simulation using the hardware description language VHDL, then they are implemented on a Xilinx Spartan type FPGA card using the XILINX software.

Design, optimization and Real Time implementation of a new Embedded Chien Search Block for Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes on FPGA Board

The development of error correcting codes has been a major concern for communications systems. Therefore, RS and BCH (Reed-Solomon and Bose, Ray-Chaudhuri and Hocquenghem) are effective methods to improve the quality of digital transmission. In this paper a new algorithm of Chien Search block for embedded systems is proposed. This algorithm is based on a factorization of error locator polynomial. i.e, we can minimize an important number of logic gates and hardware resources using the FPGA card. Consequently, it reduces the power consumption with a percentage which can reach 40 % compared to the basic RS and BCH decoder. The proposed system is designed, simulated using the hardware description language (HDL) and Quartus development software. Also, the performance of the designed embedded Chien search block for decoder RS\BCH (255, 239) has been successfully verified by implementation on FPGA board.

Iterative Soft-Input Soft-Output Bit-Level Reed-Solomon Decoder Based on Information Set Decoding

In this paper, a bit-level decoder is presented for soft-input soft-output iterative decoding of Reed-Solomon (RS) codes. The main aim for the development of the proposed algorithm is to reduce the complexity of the decoding process, while yielding a relatively good error correction performance, for the efficient use of RS codes. The decoder utilises information set decoding techniques to reduce the computational complexity cost by lowering the iterative convergence rate during the decoding process. As opposed to most iterative bit-level soft-decision decoders for RS codes, the proposed algorithm is also able to avoid the use of belief propagation in the iterative decoding of the soft bit information, which also contributes to the reduction in the computational complexity cost of the decoding process. The performance of the proposed decoder is investigated when applied to short RS codes. The error correction simulations show the proposed algorithm is able to yield a similar performance to that of the Adaptive Belief Propagation (ABP) algorithm, while being a less complex decoder.

Design, optimization and Real Time implementation of a new Embedded Chien Search Block for Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes on FPGA Board.

The development of error correcting codes has been a major concern for communications systems. Therefore, RS and BCH (Reed-Solomon and Bose, Ray-Chaudhuri and Hocquenghem) are effective methods to improve the quality of digital transmission. In this paper a new algorithm of Chien Search block for embedded systems is proposed. This algorithm is based on a factorization of error locator polynomial. i.e, we can minimize an important number of logic gates and hardware resources using the FPGA card. Consequently, it reduces the power consumption with a percentage which can reach 40 % compared to the basic RS and BCH decoder. The proposed system is designed, simulated using the hardware description language (HDL) and Quartus development software. Also, the performance of the designed embedded Chien search block for decoder RS\BCH (255, 239) has been successfully verified by implementation on FPGA board.

High Throughput Low Complexity and Low Power ePiBM RS Decoder Using Fractional Folding

This brief proposes a novel generalized Fractional Folding (FF) architecture for digital signal processing integrated circuits. With this new structure, a Fractional Folding based enhanced Parallel Inversionless Berlekamp-Massey (FF-ePIBM) Reed-Solomon Decoder is presented of which the number of processing element (PE) can be reduced to only one, resulting in ultra-low hardware complexity. The FF-ePIBM VLSI architecture can greatly reduce the hardware cost by about 60% compare to the fully expanded parallel ePIBM architecture. With FF-ePIBM architecture, syndrome calculation (SC) block and Chien search & error evaluation (CSEE) block are able to operate at a lower frequency resulting in about 14.8% power saving. A polyphase clock signal is needed in order to achieve fractional folding function according to specific fractional-factor. It is generated from Delay Locked Loop (DLL) at little or no extra cost in different SoCs. To maximize the throughput of decoder, pipelined architecture is adopted to optimize critical path delay. The RS (255, 239) decoder with FF-ePIBM architecture is finally implemented with 40nm CMOS technology. The synthesized results demonstrate that the decoder has a gate count of 12.9k and can operate at 3.1GHz to achieve a highest throughput of 24.8Gb/s and a best TSNT FoM value of 592 to this date.

Shaping duo binary turbo-coded BICM scheme for JPWL image transmission using a link adaptation strategy over wireless channels

In order to guarantee a robust transmission of JPWL (JPEG Wireless: Joint Photographic Experts Group Wireless) images through time and frequency selective wireless channels, an efficient adaptive communication strategy is proposed. It is based on an optimization of a closed-loop adaptive multiple-input multiple-output, orthogonal frequency division multiplexing (MIMO-OFDM) scheme associated with a shaping BICM (bit-interleaved coded modulation) technique composed of a duo binary turbo code (DBTC), high-order modulations such as 64–256 QAM (Quadrature Amplitude Modulation) and a shaping code. According to the CSI (channel state information) knowledge at the transmitter side, an algorithm based on unequal error protection (UEP) and unequal power allocation (UPA) is used to select the transmitter key parameters (source/channel encoder rate, modulation order, power, number of quality layers and number of iterations of the Turbo decoder) to achieve the target Quality of Service (QoS). The proposed DBTC-shaping BICM scheme reaches a shaping gain of 1.2 dB for a 256 QAM modulation over a SISO Gaussian channel, whereas only 0.7 dB of shaping gain can be achieved in a scheme that uses the LDPC shaping BICM scheme for the same modulation order. Based on a DBTC shaping BICM scheme and an adaptive algorithm, the proposed MIMO-OFDM strategy achieves better performance compared to a strategy using an iterative process between an RS (Reed-Solomon) and arithmetic decoders. As a result, and on the one hand, a gain of 5.38 dB can be achieved in terms of PSNR (peak signal-to-noise ratio). On the other hand, a gain of 78% in terms of power consumption is obtained for the same QoS level. Moreover, the adaptive number of iterations in the proposed strategy can minimize the computational complexity of the turbo decoding compared to a scheme using four iterations whatever the channel conditions.

An Even/Odd Error Detection Based Low-Complexity Chase Decoding for Low-Latency RS Decoder Design

This letter presents a modified low-complexity chase (LCC) algorithm, where a fewer number of vectors can be tested with minor error correction performance degradation. The proposed LCC decoding pre-determines whether the number of errors in the received codeword is even or odd, and it processes only necessary test vectors. As a result, the number of test vectors can be reduced by half compared to the conventional LCC decoding. The Reed-Solomon (255,239) decoder with the proposed LCC algorithm has been implemented using 65nm CMOS process. The hardware implementation results show that the proposed decoder shows 48.5% reduced latency with 0.06 dB of coding gain decrease at $\mathbf {10^{-6}}$ codeword error rate compared to the state-of-the-art LCC decoder.

Design and Implementation of RS(450, 406) Decoder

Nowadays, in the field of data transmission between receiver and transmitter, the Reed Solomon code is used very frequently. FEC codes have two foremost and influential operations: (1) calculating parity symbols at the encoder side and (2) transmitting message symbols with parity symbols and decoding the received codeword at the second side by using the decoding algorithms. Gigabit automotive ethernet is used in the automotive car to provide better bandwidth for every kind of applications to connect functional components of the vehicles. This error correction technique is used in the gigabit automotive ethernet to reduce the channel noise during data transmission. RS (450, 406) is a powerful error correction techniques used in automotive ethernet. This paper focused only on the analysis of Reed Solomon decoding. Reed Solomon decoding is more efficient decoding techniques for correcting both burst and random errors. The critical steps of the Reed Solomon decoding are to solve the error evaluator and error calculator polynomial, which is also known as KES solver.

On fast Fourier transform-based decoding of Reed-Solomon codes

Reed-Solomon (RS) codes is a popular class of codes that have been implemented in many practical systems. Recently, a fast approach to the error decoding of RS codes based on fast Fourier transform (FFT) was invented. In this work, we derive the key equation based on the Lagrange polynomial and then present erasure-and-error decoding of an (n; k) RS code. This decoding algorithm can simultaneously correct up to v errors and f erasures when 2v + f < n − k + 1. The decoding complexity is with only O(n log n + (n − k) log2(n − k)).

Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures

This brief introduces a new method to compute in parallel the roots of a polynomial locator of degree four in a Reed-Solomon decoder. The novelty of this brief is the introduction of an algorithm that transforms the polynomial locator obtained with the Peterson-Gorenstein-Zierler's algorithm into an equivalent one that allows a direct search for the four roots that indicate the location of the symbols in error. This new solution improves a previous approach proposed in the literature for a quadruple-error-correction decoder (QEC) that requires a cubic aid equation. This previous solution does not work in the cases in which the cubic aid does not have a solution. In contrast, the proposal of this brief works in 100% of cases (with t ≤ 4) as it solves an equivalent polynomial. This new algorithm allows two different implementations: a fully parallel architecture which provides an extremely low latency at an extra area cost, and a fully serial architecture with less area, but a higher latency.

Comparison of FPGA and Microcontroller Implementations of an Innovative Method for Error Magnitude Evaluation in Reed–Solomon Codes

Reed–Solomon (RS) codes are one of the most used solutions for error correction logic in data communications. RS decoders are composed of several blocks: among them, many efforts have been made to optimize the error magnitude evaluation module. This paper aims to assess the performance of an innovative algorithm introduced in the literature by Lu et al. under different systems configurations and hardware platforms. Several configurations of the encoded message chosen between those typically used in different applications have been designed to be run on an FPGA (field programmable gate array) device and an MCU (microcontroller unit). The performances have been evaluated in terms of resource usage and output delay for the FPGA and in terms of code execution time for the MCU. As a benchmark in the analysis, the well-established Forney’s method is exploited: it has been implemented in the same configurations and on the same hardware platforms for a proper comparison. The results show that the theoretical finding are fully confirmed only in the MCU implementation, while on FPGA, the choice of one method with respect to the other depends on the optimization feature (i.e., time or area) that has been decided as a preference in the specific application.

VLSI Architectures for Reed–Solomon Codes: Classic, Nested, Coupled, and Beyond

Classic Reed-Solomon (RS) codes and binary Bose-Chaudhuri-Hocquenghem (BCH) codes, which can be considered as a special case of RS codes, are utilized for error correction in numerous systems, such as Flash memories, optical communications, wireless communications, magnetic storage, and deep-space probing. Additionally, RS and BCH codes are interleaved/nested to form high-gain coding schemes, including product and product-like codes and the recent generalized integrated interleaved codes, which are among the most promising candidates to address the hyper-speed and excellent-correction-capability requirements posed by next-generation terabit/s digital communications and storage. In recent developments, RS codes are also split/nested/coupled to form locally recoverable erasure codes and minimum storage regenerating codes that substantially improve the efficiency of failure recovery and enable the continued scaling of large-scale distributed storage. In this article, prominent decoder architectures for classic RS/BCH codes are elaborated and the fundamental mathematical reformulations leading to the architectures are explained. Then the challenges and recent advancements on the decoder design of nested RS/BCH codes are highlighted. Erasure-correcting RS decoders for failure recovery are also briefly discussed. The goal of this article is to provide comprehensive understanding of state-of-the-art VLSI architectures for classic RS/BCH codes and introduce the most recent architectures for new coding schemes built by nesting/coupling RS/BCH codes for emerging applications.

Efficient Architectures for Generalized Integrated Interleaved Decoder

Generalized integrated interleaved (GII) codes allow localized decoding of short sub-codewords. They are essential to hyper-speed data storage, communications, and continued scaling of distributed storage. Sub-codewords, which are usually Reed–Solomon (RS) or BCH codewords, are nested to generate codewords of higher correction capabilities. If the decoding of individual sub-codewords fails, the higher-order syndromes from the nested codewords are utilized to correct more errors. GII decoder design faces many challenges. The major ones include: 1) high-speed nested decoding utilizing the higher-order syndromes; 2) efficient updating of higher-order syndromes after sub-codewords are corrected; 3) computation of nested syndromes and matrix inversion for converting them to higher-order sub-codeword syndromes; and 4) efficient architectures capable of addressing the variable correction capabilities of the nested codewords. This paper proposes novel algorithmic reformulations and architectural transformations to address each bottleneck. For an example, GII code that has the same rate and length as eight un-nested (255, 223) RS codes, the proposed GII decoder achieves more than seven orders of magnitude improvement in error-correcting performance with less than 30% area overhead compared to the RS decoder. With a critical path of seven XOR gates, the proposed decoder can easily achieve more than 40 GB/s throughput.

Modelling the OFDM-based PHY Layer in SoC for Visible Light Communication

In this paper, we report a System-on-Chip (SoC) architecture for OFDM-based Visible Light Communication (VLC). The OFDM block was implemented as VLC PHY layer. The OFDM block comprises of transmitter and receiver. In transmitter block, there are Reed-Solomon encoder, modulator, IFFT, and preamble generator. While in receiver block, there are Reed-Solomon decoder, demodulator, FFT, and synchronizer. In SoC, these blocks are designed as IP cores. The industry standard AXI4-Stream protocol was used for data exchange between IP cores. The OFDM model in SoC was verified by comparing with a MATLAB simulation.

On the Construction of Composite Finite Fields for Hardware Obfuscation

Hardware obfuscation is a technique that modifies the circuit to hide the functionality. Obfuscations through algorithmic modifications add protection in addition to circuit-level techniques, and their effects on the data paths can be analyzed and controlled at the architectural level. Many error-correcting coding and cryptography algorithms are based on finite field arithmetic. For the first time, this paper proposes a hardware obfuscation scheme achieved through varying finite field constructions and primitive element representations. Also the variations are effectively transformed to bit permuters controlled by obfuscation keys to achieve high level of security with very small complexity overheads. To illustrate the effectiveness, the proposed scheme is applied to obfuscate Reed-Solomon decoders, which are broadly used in communication and storage systems. For a (255, 239) RS decoder over finite field $GF(256)$GF(256), the proposed scheme achieves 1239 bits of independent obfuscation key with 4.4 percent area overhead, while yielding no penalty on the throughput and only one extra clock cycle of latency.

An α-factor architecture for RS decoder implemented on 90 nm CMOS technology for computer computing applications devices

In Computing devices in the world wide, where number of computing and communication systems are increased rapidly. In the channel noise has greater impact on the messages or data transmitted through the wired/wireless network. The Reed–Solomon (RS) decoder plays a vital role in removing the error from the received messages or data. The RS decoder has four main blocks, namely, Syndrome Computation (SC) block, Key Equation Solver (KES) block, Chien Search (CS) block and Forney Algorithm (FA) block. The researchers have thrown a number of works on each and every block of RS decoder. Moreover, the parallel and pipelined RS decoder shows a greater improvement in terms of gate element, latency, coding gain and throughput. Although this architecture has higher performance gain, the computation complexity in the SC block is not addressed. This paper presents an efficient architecture to compute the α-factor of SC blocks in RS decoder. The proposed RS decoder is developed using Verilog HDL (Hardware Description Language) and synthesized in Synopsys Design Compiler (DC). The proposed architecture is implemented in 90 nm CMOS technology and the results are evaluated in terms of gate count, clock rate, latency and throughput. The evaluated results of the proposed decoder show a remarkable improvement when compared with a conventional RS decoder.