Redundant Through-silicon Vias Research Articles

TRUST: Through-Silicon via Repair Using Switch Matrix Topology

To address the demand for memory scaling capabilities, three-dimensional integrated circuits (3D-ICs) based on short and dense through-silicon vias (TSVs) have been introduced. However, the defects of TSVs considerably influence the yield and reliability of 3D-ICs. For this reason, TSV repair using switch matrix topology (TRUST) is proposed in this paper. TRUST adopts a switch matrix, which has a high routing flexibility, to realize TSV connections. Consequently, a 100% repair rate can be achieved for the 3D-ICs that have faulty TSVs smaller than or equal to redundant TSVs. Furthermore, TRUST utilizes content-addressable memories in built-in self-repair to identify TSV repair paths via a simple TSV repair path search algorithm. For this reason, TRUST can be applied to repair manufacturing and aging defects of TSVs. Nevertheless, TRUST can be applied with reasonable area and delay overheads, such as 58.3% area reduction and 55.1% delay reduction compared to the only conventional TSV repair architecture that can achieve the optimal repair rate. In addition, the area ratios in high bandwidth memory (HBM) and HBM2 are only 5.3% and much smaller than 0.1%, respectively. The advantages are experimentally verified.

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the through-silicon vias (TSVs) defect tend to be clustered, reducing the yield of 3-D integrated circuit significantly. To tackle this fault clustering problem, the existing TSV repair methods adopt the TSV redundancy idea, which brings a major cost to 3-D integration. In this brief, a honeycomb-TDMA TSV design is proposed to mitigate the impact of multiple clustered faults without the need of redundant TSVs (RTSVs), thereby decreasing the area overhead and enhances the yield. The yield of the honeycomb-TDMA architecture can achieve 91.38%-99.67% for different benchmark circuits from IWLS 2005, which has the highest yield. Furthermore, our design achieves total additional hardware (timing delay overhead) reduction by 83.70%-86.85% (46.01%-55.96%), 66.89%-73.25% (29.41%-38.49%), 68.02%-74.20% (41.40%-52.20%), 60.60%-68.18% (18.09%-33.18%), and 75.86%-80.52% (3.05%-20.91%), respectively, compared with router-based, ring-based, group-based, cellular-based, and honeycomb-based methods. Therefore, the proposed architecture is the best choice in terms of yields, hardware overhead, and timing delay.

A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology

Through-silicon-vias (TSVs) are prone to defects during the manufacturing process, which pose yield challenges for three dimensional integrated circuits (3D-ICs). The area per TSV is too great to be ignored, and in order to not use any redundant TSVs, a chain-type time division multiplexing access (TDMA)-based fault tolerance technique is proposed. However, a double-TSV structure is used per group, resulting in a significant TSV hardware overhead under a given large-scaled circuit design. Furthermore, it is impossible for the chain-TDMA scheme to plan the rerouting path for the right-hand-most TSV per group, resulting in a decrease in the repair rate per TSV group as well as in the whole TSV yield. In the proposed technique, we bundle six TSVs per group in a honeycomb pattern and the TSVs on the edges are connected to each other, enhancing the repair rate per group as well as the whole TSV yield. Subsequently, an architecture based on the proposed technique is designed, evaluated, and validated on logic-on-logic 3D IWLS'05 benchmark circuits using 45 nm TSMC technology. The proposed technique is found to reduce the area overhead by 87.95-90.42 percent, compared to the chain-TDMA scheme, which results in a yield of 96.90-99.09 percent.

CC-RTSV: Cross-Cellular Based Redundant TSV Design for 3D ICs

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring increases the faulty TSVs (FTSV), i.e., the TSV defects tend to be clustered which significantly reduces the yield of three-dimensional integrated circuits (3D-ICs). To resolve the clustered TSV faults, router-based and ring-based redundant TSV (RTSV) architecture were proposed. However, the repair rate is low and the hardware overhead is high. In this paper, we propose a novel cross-cellular based RTSV architecture to utilize the area more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has higher repair rate as well as more cost-effective overhead, compared with router-based and ring-based methods.

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the faulty TSV increases, i.e., the TSV defects tend to be clustered, which significantly reduces the yield of 3-D integrated circuit. To resolve the clustered TSV faults, router-based, ring-based, group-based, and cellular-based redundant TSV (RTSV) architectures were proposed. However, the repair rate is low and the hardware overhead as well as delay overhead is high. In this article, we propose a honeycomb-based RTSV architecture to utilize the area and delay more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has a 99.84% repair rate for uniform faults and an 81.42% repair rate for highly clustered faults. The proposed design achieves a 51.66% reduction of hardware overhead compared with the router-based design and a 20.69%, 46.93%, 34.17%, and 11.15% reduction of total delay compared with ring-based, router-based, group-based, and cellular-based methods, respectively.

Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for Heterogeneous 3-D SoCs

Three-dimensional integration, employing through-silicon vias (TSVs), improves the system-on-chip (SoC) performance. However, redundancy schemes are required to cope with the relatively poor TSV manufacturing yield. Existing redundancy schemes do not exploit technological heterogeneity between the dies. Hardware costs can differ for the individual dies. This demands asymmetrical schemes with low complexity in costly mixed signal or RF dies. Furthermore, redundant TSVs are only used in the case of a defect. In the most probable case of correct manufacturing, they are unused. Another emerging technique using redundant lines is low-power coding (LPC). This paper presents a hybrid TSV redundancy technique based on coding, which can be used for LPC and for yield enhancement. Furthermore, the approach is strongly asymmetric. In case of a fault, a configuration is only required for the encoder or decoder located in the cheaper die, while in the costly die, a minimal set of XOR gates is sufficient. A case study for an existing heterogeneous SoC shows that the proposed technique decreases area overhead and power consumption compared to the best previous technique by over 69 % and 33%, respectively.

A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults

Three-dimensional integrated circuits (3-D ICs), which feature many benefits, such as high bandwidth and a high degree of integration, have recently received considerable attention from the semiconductor industry. However, these chips feature through-silicon vias (TSVs), which vertically connect multiple dies, and these TSVs may fail, resulting in a decreased yield. Unfortunately, previously proposed methods to repair TSVs cannot handle certain failure patterns. For example, existing techniques cannot repair clustered TSV faults, which commonly occur in practice. Furthermore, the number of signal TSVs typically determines the number of redundant TSVs, which may result in wasteful and redundant TSVs. In this paper, a new TSV repair scheme is proposed that replaces defective TSVs with redundant TSVs by utilizing the architecture of a cube, which can replace any face with any of the other faces. Both signal TSVs and redundant TSVs are placed in the face of cube, so any faulted TSVs can be replaced with redundant TSVs. The experimental results indicate that the new method guarantees 100% coverage with any number of signal TSVs and redundant TSVs.

A New Cellular-Based Redundant TSV Structure for Clustered Faults

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process, which greatly reduces the yield of 3-D-ICs. The basic method to repair faulty TSVs (FTSVs) is to transfer the signals on FTSVs through regular TSVs. Many redundant TSV (RTSV) structures have been proposed to repair uniformly distributed FTSVs. For clustering FTSVs, a router-based RTSV structure appears to be a good scheme. But it is not an economical method, since the structure consumes many more hardware resources than normal structures. In this paper, we propose a cellular-based RTSV structure to utilize hardware resources more efficiently for a higher yield. We propose a corresponding algorithm for recovery-route searching. Simulation results show that for 1E6 TSVs and a TSV failure rate of 0.01%, our design consumes only 4.5% more area of all STSVs to achieve a yield above 99.9%. We compare our structure with several other designs and demonstrate the cost-effectiveness of the proposed technique.

TSV Repair Architecture for Clustered Faults

The poor quality of the die stacking process for 3-D integrated circuits can result in the failure of the process in the through-silicon-vias (TSVs) in dense regions. Previous works use the same number of redundant TSVs and architectures that do not consider the TSV density. A repair architecture and an appropriate number of redundant TSVs, which are chosen considering the TSV density, are required for an improved repair rate. This paper proposes a method that demonstrates such an architecture and calculates the required number of TSVs. The method has a high repair rate for clustered faults, and wire-length problems are solved using the shift-based repair method.

A Novel Approach for Using TSVs As Membrane Capacitance in Neuromorphic 3-D IC

An advanced neurophysiological computing system can incorporate a 3-D integration system composed of emerging nano-scale devices to provide massive parallelism having high speed, low cost, and energy efficient hardware implementation. Due to process technology constraints, a certain amount of redundant through silicon vias (TSVs) and dummy TSVs are always required in a 3-D integrated system. In this paper, we propose to use these redundant and dummy TSVs to supply the neuronal membrane capacitance that maps the membrane electrical activity in a hybrid 3-D neuromorphic system. This proposition could also serve the need of neuronal ion transportation dynamics. We also investigate two new methodologies that could significantly enhance the TSV capacitance in a 3-D neuromorphic system. The capacitance of these enhanced TSVs is studied with analytical models; the accuracy of the models are evaluated against 3-D field extracted values. The advantage of using the TSVs to mimic membrane capacitance in a 3-D neuromorphic chip is demonstrated through comparisons of both silicon area and energy consumption against their 2-D counterpart designs.

An Efficient Fault Tolerance Technique for Through-Silicon-Vias in 3-D ICs

Three-dimensional integrated circuits (3D-ICs) based on Through-Silicon-Vias (TSVs) interconnection technology appeared as a viable solution to overcome problems of cost, reliability, yield and stacking area. In order to be commercially feasible, the 3D-IC yield must be as high as possible, which requires a tested and reparable TSVs. To overpass this challenge, an integration of interconnect built-in self-test (IBIST) methodology for 3D-IC is given in the aims to test the defectives TSVs. Once the interconnection has been tested, the result extracted from IBIST initiate the repairing defectives TSVs based on the built-in self-repair (BISR) structure. This paper superposed two fault tolerance techniques in particularly the redundant TSV and the time division multiplexing access (TDMA) in case of multi defectives TSV. This novel repair architecture increase the yield of 3D-ICs in a high failure rate. It leads to 100% reparability for 30% failure rate. A parallel processing approach of the proposed structure is presented to accelerate the test and repair operations. Achieved experimental results with the proposed methodology scheme show a good performance in terms of repair rate and yield.

Architecture of Ring-Based Redundant TSV for Clustered Faults

Three-dimensional integrated circuits (3-D-ICs) that employ the through-silicon vias (TSVs) vertically stacking multiple dies provide many benefits, such as high density, high bandwidth, and low power. However, the fabrication and bonding of TSVs may fail because of many factors, such as the winding level of the thinned wafers, the surface roughness and cleanness of silicon dies, and bonding technology. To improve the yield of 3-D-ICs, many redundant TSV (RTSV) architectures were proposed to repair 3-D-ICs with faulty TSVs. These methods reroute the signals of faulty TSVs to other regular TSV or RTSV. In practice, the faulty TSVs may cluster because of imperfect bonding technology. To resolve the problem of clustered TSV faults, router-based RTSV architecture was the first proposed to pay attention to it. Their method enables faulty TSVs to be repaired by RTSVs that are farther apart. However, to repair some rarely occurring defective patterns, their method requires too much area. In this paper, we propose a ring-based RTSV architecture to utilize the area more efficiently as well as to maintain high yield. Assume that the size of the TSVs is 1 $\mu \text{m}$ . Simulation results show that for a given number of TSVs ( $8 \times 8$ ) and TSV failure rate (1%), our design achieves 58.9% area reduction of MUXes per signal, 54.6% total area reduction per signal, and 50.54% total wire length reduction while the yield of our ring-based RTSV architectures can still maintain 98.47%–99% as compared with the router-based design. Furthermore, the shifting length of our ring-based RTSV architecture is at most 1, which guarantees at most one MUX-delay timing overhead of each signal.

On Effective Through-Silicon Via Repair for 3-D-Stacked ICs

3-D-stacked integrated circuits (ICs) that employ through-silicon vias (TSVs) to connect multiple dies vertically have gained wide-spread interest in the semiconductor industry. In order to be commercially viable, the assembly yield for 3-D-stacked ICs must be as high as possible, requiring TSVs to be reparable. Existing techniques typically assume TSV faults to be uniformly distributed and use neighboring TSVs to repair faulty ones, if any. In practice, however, clustered TSV faults are quite common due to the fact that the TSV bonding quality depends on surface roughness and cleanness of silicon dies, rendering prior TSV redundancy solutions less effective. Furthermore, existing techniques consume a lot of redundant TSVs that are still costly in the current TSV process. This inefficient TSV redundancy can limit the amount of TSVs that is allowed to use and may even become the obstacle to commercial production. To resolve this problem, we present a novel TSV repair framework, including a hardware redundancy architecture that enables faulty TSVs to be repaired by redundant TSVs that are farther apart, the corresponding repair algorithm and the redundancy architecture construction. By doing so, the manufacturing yield for 3-D-stacked ICs can be dramatically improved, as demonstrated in our experimental results.

Fault-Tolerant Vertical Link Design for Effective 3D Stacking

Recently, 3D stacking has been proposed to alleviate the memory bandwidth limitation arising in chip multiprocessors (CMPs). As the number of integrated cores in the chip increases the access to external memory becomes the bottleneck, thus demanding larger memory amounts inside the chip. The most accepted solution to implement vertical links between stacked dies is by using Through Silicon Vias (TSVs). However, TSVs are exposed to misalignment and random defects compromising the yield of the manufactured 3D chip. A common solution to this problem is by over-provisioning, thus impacting on area and cost. In this paper, we propose a fault-tolerant vertical link design. With its adoption, fault-tolerant vertical links can be implemented in a 3D chip design at low cost without the need of adding redundant TSVs (no over-provision). Preliminary results are very promising as the fault-tolerant vertical link design increases switch area only by 6.69% while the achieved interconnect yield tends to 100%.

Micronetworking: reliable communication on 3D integrated circuits

A model is proposed to mitigate the communication problem in 3D integrated circuits caused by the breaks at the through-silicon vias (TSVs). Using a low-complexity network, the introduction of redundant TSVs makes it possible to reroute around breaks to maintain effective communication between layers.