Redundant Number Representation Research Articles

Non-power positional number representation systems, bijective numeration, and the Mesoamerican discovery of zero

Pre-Columbian Mesoamerica was a fertile crescent for the development of number systems. A form of vigesimal system seems to have been present from the first Olmec civilization onwards, to which succeeding peoples made contributions. We discuss the Maya use of the representational redundancy present in their Long Count calendar, a non-power positional number representation system with multipliers 1, 20, 18 × 20, …, 18 × 20n. We demonstrate that the Mesoamericans did not need to invent positional notation and discover zero at the same time because they were not afraid of using a number system in which the same number can be written in different ways. A Long Count number system with digits from 0 to 20 is seen later to pass to one using digits 0 to 19, which leads us to propose that even earlier there may have been an initial zeroless bijective numeration system whose digits ran from 1 to 20. Mesoamerica was able to make this conceptual leap to the concept of a cardinal zero to perform arithmetic owing to a familiarity with multiple and redundant number representation systems.

An alternative carry-save arithmetic for new generation field programmable gate arrays

In this work, a double carry-save addition operation is proposed, which is efficiently synthesized for 6-input LUT-based field programmable gate arrays (FPGAs). The proposed arithmetic operation is based on redundant number representation and provides carry propagation-free addition. Using the proposed arithmetic operation, a compact and fast multiply and accumulate unit is designed. To our knowledge, the proposed design provides the fastest multiply-add operation for 6-input LUT-based FPGA systems. A finite impulse response filter implementation is given to show the performance of the proposed structure. The proposed implementation provides a dramatic performance increase, which is at least 2 times faster than conventional binary multiply-add implementations.

Redundancy of minimal weight expansions in Pisot bases

Motivated by multiplication algorithms based on redundant number representations, we study representations of an integer n as a sum n=∑kεkUk, where the digits εk are taken from a finite alphabet Σ and (Uk)k is a linear recurrent sequence of Pisot type with U0=1. The most prominent example of a base sequence (Uk)k is the sequence of Fibonacci numbers. We prove that the representations of minimal weight ∑k|εk| are recognised by a finite automaton and obtain an asymptotic formula for the average number of representations of minimal weight. Furthermore, we relate the maximal number of representations of a given integer to the joint spectral radius of a certain set of matrices.

A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams

This paper introduces a systematic approach to designing high-performance parallel adders based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe addition algorithms at various levels of abstraction. A high-level CTD represents a network of coarse-grained components associated with word-level operands, whereas a low-level CTD represents a network of primitive components that can be directly mapped onto physical devices. The level of abstraction in circuit representation can be changed by decomposition of CTDs. We can derive possible variations of adder structures by decomposing a high-level CTD into low-level CTDs in a formal manner. In this paper, we focus on an application of CTDs to the design of redundant arithmetic adders with limited carry propagation. For any redundant number representation, we can obtain the optimal adder structure by trying every possible CTD decomposition and CTD-variable encoding. The potential of the proposed approach is demonstrated through an experimental synthesis of Redundant-Binary (RB) adders with CMOS standard cell libraries. We can successfully obtain RB adders that achieve an about 30-40% improvement in terms of power-delay product compared with conventional designs.

A New Systolic Architecture for Modular Division

A new systolic architecture for modular division is proposed in this paper. The architecture is based on a new hardware algorithm for modular division that is extended from the plus-minus algorithm for the greatest common divisor computation. Both the area complexity and the time complexity of the new architecture are linear with respect to the operand bit length. Compared to the architecture using a redundant number representation proposed by Kaihara and Takagi, the new architecture allows a doubled throughput due primarily to the greatly reduced critical path delay, while the area is only about 20 percent larger. Moreover, it is shown that, with a small addition to the control logic, the architecture can also be used to perform Montgomery modular multiplication, thereby efficiently realizing a unified modular multiplier/divider

Leading guard digits in finite precision redundant representations

Redundant number representations are generally used to allow constant time additions, based on the fact that only bounded carry-ripples take place. But, carries may ripple out into positions which may not be needed to represent the final value of the result and, thus, a certain amount of leading guard digits are needed to correctly determine the result. Also, when cancellation during subtractions occurs, there may be nonzero digits in positions not needed to represent the result of the calculation. It is shown here that, for normal redundant digit sets with radix greater than two, a single guard digit is sufficient to determine the value of such an arbitrary length prefix of leading nonzero digits. This is also the case for the unsigned carry-save representation, whereas two guard digits are sufficient, and may be necessary, for additions in the binary signed-digit and 2's complement carry-save representations. Thus, only the guard digits need to be retained during sequences of additions and subtractions. At suitable points, the guard digits may then be converted into a single digit, representing the complete prefix.

An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding

Redundant and hybrid-redundant number representations are used extensively to speed up arithmetic operations within general-purpose and special-purpose digital systems, with the latter (containing both redundant and nonredundant digits) offering cost advantages over fully redundant systems. We use weighted bit-set (WBS) encoding as a paradigm for uniform treatment of five previously studied variants of hybrid-redundant systems. We then extend the class of hybrid-redundant numbers to coincide with the entire set of canonical WBS numbers by allowing an arbitrary nonredundant position, heretofore restricted to ordinary bits (posibits), to hold a negatively weighted bit (negabit). This flexibility leads to interesting and useful symmetric variants of hybrid-redundant representations. We provide a high-level circuit design, based solely on binary full-adders, for a constant-time universal hybrid-redundant adder capable of producing a canonical WBS-encoded sum of two canonical WBS (or extended hybrid) numbers. This is made possible by the use of conventional binary full-adders for reducing any collection of three posibits and negabits, where negabits use an inverted encoding. We compare our adder to previous designs, showing advantages in speed, cost, and regularity. Furthermore we explore representationally closed addition schemes, holding the benefit of greater regularity and reusability, and provide high-level representationally closed designs for all the previously studied variants of hybrid redundancy and for the new symmetric variants introduced here. Finally, we present a new functionality for a conventional (4; 2) compressor in combining any collection of five equally weighted negabits and posibits, and show its utility in the design of multipliers for extended hybrid-redundant numbers.

Digit Pipelined Arithmetic for 3-D Massively Parallel Optoelectronic Circuits

A concept for a future integer arithmetic unit suitable for a realization with 3-D optoelectronic very large scale integrated (VLSI) circuits is presented. Due to the use of optical interconnections running vertically to the circuit's surface no pin limitation is given. This allows massively parallelism and a higher throughput performance than in all-electronic solutions. To exploit the potential of optical interconnections in VLSI systems efficiently well-adapted low-level algorithms and architectures have to be developed. This is demonstrated for a pipelined arithmetic unit using a redundant number representation. A transistor layout for the optoelectronic circuits is given as well as a specification for the necessary optical interconnection scheme linking the circuits with free-space optics. It is shown that the throughput can be increased by a factor of 10 to 50 compared to current all-electronic processors by considering state-of-the-art optical and optoelectronic technology. Furthermore we present results we gained by investigations on a first realized optoelectronic VLSI test chip.

Signed-digit arithmetic for optical computing: digit grouping and pixel assignment for spatial encoding

Novel fully parallel one-step adders that use the redundant signed-digit number representation are proposed for optical computing. A new method for spatially encoding the signed-digit is proposed based on digit grouping and pixel assignment. The scheme of digital grouping of the signed-digit numbers enables a huge reduction of the number of symbolic substitution computation rules involved in the arithmetic computations and consequently increases the speed of arithmetic operations. Furthermore, the proposed spatial encoding scheme effectively increases the space bandwidth product of the spatial light modulators and decreases the size of the matched spatial filters of the optical system.

Optical arithmetic processing using improved redundant binary algorithms

Carry-free parallel arithmetic computing using redundant binary number representation is exploited. Based on the original two-step algorithm, several improved algorithms including modified two-step, one- step, canonical, and three-input algorithms are proposed to increase processing speed and simplify the implementation system. The symbolic substitution rules for redundant binary addition are represented by binary logic operations and realized using optical space-variant binary logic gates. The proposed optical architecture is suitable for realizing both binary logic and arithmetic operations.

High efficiency redundant binary number representations for parallel arithmetic on optical computers

A family of redundant binary number representations, obtained by generalization of the RB (redundant binary) number representation, is introduced. All these number representations are suitable for optical computing and have properties similar to the RB representation. In particular, the p-RB (packed redundant binary) number representation introduced in this work has efficiency greater than both RB and MSD (modified signed digit) representations. With p-RB numbers the algebraic sum is always permitted in constant time for any efficiency value. p-RB representations also fit in a natural way the 2's complement binary number system. Symbolic substitution truth tables for the algebraic sum and several examples of computation are also given.

High-speed area-efficient multiplier design using multiple-valued current-mode circuits

Presents a very-large-scale-integration (VLSI)-oriented high-speed multiplier design method based on carry-propagation-free addition trees and a circuit technique, so-called multiple-valued current-mode (MVCM) circuits. The carry-propagation-free addition method uses a redundant digit set such as /spl lcub/0,1,2,3/spl rcub/ and /spl lcub/0,1,2,3,4/spl rcub/. The number representations using such redundant digit sets are called redundant positive-digit number representations. The carry-propagation-free addition is written by three steps, and the adder can be designed directly and efficiently from the algorithm using MVCM circuits. The designed multiplier internally using the MVCM parallel adder with the digit set /spl lcub/0,1,2,3/spl rcub/ in radix 2 has attractive features on speed, regularity of the structure, and reduced complexities of active elements and interconnections. A prototype CMOS integrated circuit of the MVCM parallel adder has been implemented, and its stable operation has been confirmed. Other possible schemes of multipliers with redundant digit sets using MVCM technology are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Hybrid signed-digit number systems: a unified framework for redundant number representations with bounded carry propagation chains

A novel hybrid number representation is proposed. It includes the two's complement representation and the signed-digit representation as special cases. The hybrid number representations proposed are capable of bounding the maximum length of carry propagation chains during addition to any desired value between 1 and the entire word length. The framework reveals a continuum of number representations between the two extremes of two's complement and signed-digit number systems and allows a unified performance analysis of the entire spectrum of implementations of adders, multipliers and alike. We present several static CMOS implementations of a two-operand adder which employ the proposed representations. We then derive quantitative estimates of area (in terms of the required number of transistors) and the maximum carry propagation delay for such an adder. The analysis clearly illustrates the trade-offs between area and execution time associated with each of the possible representations. We also discuss adder trees for parallel multipliers and show that the proposed representations lead to compact adder trees with fast execution times. In practice, the area available to a designer is often limited. In such cases, the designer can select the particular hybrid representation that yields the most suitable implementation (fastest, lowest power consumption, etc.) while satisfying the area constraint. Similarly, if the worst case delay is predetermined, the designer can select a hybrid representation that minimizes area or power under the delay constraint.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Redundant binary number representation for an inherently parallel arithmetic on optical computers

A simple redundant binary number representation suitable for digital-optical computers is presented. By means of this representation it is possible to build an arithmetic with carry-free parallel algebraic sums carried out in constant time and parallel multiplication in log N time. This redundant number representation naturally fits the 2's complement binary number system and permits the construction of inherently parallel arithmetic units that are used in various optical technologies. Some properties of this number representation and several examples of computation are presented.

Multi‐valued current‐mode parallel multiplier based on redundant positive‐digit number representations

AbstractThis paper proposes a new parallel multiplier based on the redundant number representation using positive digits (called redundant positive‐digit number representation, or simply PD number representation). The proposed algorithm is the fastest algorithm that can execute the multiplication of n x n digit by a time proportional to log2n. The structure is regular and is suited to LSI implementation.The proposed parallel multiplier is designed in two ways, i.e., by the multivated current mode circuit and by the binary digital circuit. Then the results are evaluated. The circuit designed by the multivated current mode, especially, has the feature that the 6‐input addition with partial product operand can be executed by the wired addition and a single‐stage parallel adder based on the PD number representation. Thus, it is demonstrated that the circuit has a high speed and can be realized with a very small number of elements and wirings. The basic circuits for the proposed parallel multiplier are constructed experimentally by 5 μm CMOS technology, and a satisfactory performance is verified.

Matrix–vector multiplication using digital partitioning for more accurate optical computing

Digital partitioning offers a flexible means of increasing the accuracy of an optical matrix-vector processor. This algorithm can be implemented with the same architecture required for a purely analog processor, which gives optical matrix-vector processors the ability to perform high-accuracy calculations at speeds comparable with or greater than electronic computers as well as the ability to perform analog operations at a much greater speed. Digital partitioning is compared with digital multiplication by analog convolution, residue number systems, and redundant number representation in terms of the size and the speed required for an equivalent throughput as well as in terms of the hardware requirements. Digital partitioning and digital multiplication by analog convolution are found to be the most efficient algorithms if coding time and hardware are considered, and the architecture for digital partitioning permits the use of analog computations to provide the greatest throughput for a single processor. To our knowledge this is the first study to propose the use of digital partitioning for optical matrix processing.

New fault tolerant techniques for residue number systems

Previously proposed error detection algorithms for the residue number system require a complete recombination. A weighted approximation via the Chinese remainder theorem is shown to be sufficient to detect 100% of single errors. This makes real-time single-error diagnosis possible, which involves up to N+2 iterations of detection (N is the number of nonredundant channels). One approach uses a scaled range of L+1+log/sub 2/ (N+1) bits for detection in contrast with full decoding of approximately=L(N+1) bits, where L is the number of bits in the largest modulus. A second method forms a redundant residue number representation of the overflow multiplier A(x), although A(x) does not need to be carried through processing operations. This permits real-time single-error diagnosis and correction with a parallel array of approximately=(N+2)/sup 2/ tables. >

Redundant CORDIC methods with a constant scale factor for sine and cosine computation

Proposes two redundant CORDIC (coordinate rotation digital computer) methods with a constant scale factor for sine and cosine computation, called the double rotation method and the correcting rotation method. In both methods, the CORDIC is accelerated by the use of a redundant binary number representation, as in the previously proposed redundant CORDIC. In the proposed methods, since the number of rotation-extensions performed for each angle is a constant, the scale factor is a constant independent of the operand. Hence, one does not need to calculate the scale factor during the computation, and can make a more efficient sine and cosine generator than that based on the previous redundant CORDIC. >

Approaching encryption at ISDN speed using partial parallel modulus multiplication

Public key systems using modulus arithmetic are quite safe mechanisms for a variety of cryptographic applications. Their main problem lies in the very long integer arithmetic. In cryptosystems usually serial-parallel multiplication is employed. Serial-parallel multiplication slows down the encryption to the order of k, where k is log 2( n), and n is the modulus. This paper demonstrates a method of using parallel multiplication schemes at the order of log( k) in combination with incomplete modulus reduction. This method calls for redundant number representations. With this background, the problem of designing a quasi optimal scheme fitting into a defined chip area is elaborated. The combination of two methods, partial parallel multiplication in redundant number representations and incomplete modulus reduction at fully completed multiplication steps only, seems to allow for RSA encryption at ISDN speed and higher.

Fast multiplier design using redundant signed-digit numbers

A high speed multiplier design is presented using redundant binary signed-digit number representation internally while the input operands and the output product are in two's complement form. The design of a carry free redundant binary signed-digit (RBSD) adder cell is presented. The multiplication algorithm uses bit-pair recording to generate the partial products. The partial products are added in the form of a binary tree using carry free RBSD adder cells. The regular structure of these adder cells results in a multiplier design that is suitable for VLSI implementation. The increased speed is achieved through the carry free addition of partial products using redundant signed-digit numbers. The use of a recoding scheme will reduce the number of rows of partial products by a factor of two. The proposed multiplier design has a multiplication time of order O(log2 n) and area-time complexity of order O(n2 log2 n) for a word length of n.