Approaching encryption at ISDN speed using partial parallel modulus multiplication

Abstract

Public key systems using modulus arithmetic are quite safe mechanisms for a variety of cryptographic applications. Their main problem lies in the very long integer arithmetic. In cryptosystems usually serial-parallel multiplication is employed. Serial-parallel multiplication slows down the encryption to the order of k, where k is log 2( n), and n is the modulus. This paper demonstrates a method of using parallel multiplication schemes at the order of log( k) in combination with incomplete modulus reduction. This method calls for redundant number representations. With this background, the problem of designing a quasi optimal scheme fitting into a defined chip area is elaborated. The combination of two methods, partial parallel multiplication in redundant number representations and incomplete modulus reduction at fully completed multiplication steps only, seems to allow for RSA encryption at ISDN speed and higher.