Reduction In Switch Count Research Articles

Five-Level Unity-Gain Active Neutral-Point-Clamped Inverters Designed Using Half-Bridges

This paper proposes two novel 5-level active neutral-point-clamped (ANPC) inverters that double the voltage gain of the conventional topology from half to unity. Each phase of the proposed topologies is constituted by three half-bridges that control a flying capacitor to generate 5 symmetrical ac voltage levels. The natural voltage balancing of dc-link and flying capacitors in the proposed topologies implies that the sensors and voltage balancing controller commonly used in the conventional ANPC inverter are no longer necessary. In addition to switch count reduction, the most noteworthy merit of the proposed topology is its ease of implementation with commercial half-bridge modules, where the design of dedicated circuit is not needed. The operation of the proposed 5-level unity-gain ANPC (5L-UG-ANPC) inverters is analyzed and validated through simulation and experimental tests.

A generalized switched‐capacitor‐based modular T‐type inverter topology with reduced switch count

SummarySwitched‐capacitor (SC)‐based multilevel inverters (MLIs) have gained great attention in renewable energy applications owing to their self‐balancing of capacitor voltage and ac voltage boosting. Using SCMLI, single‐stage dc–ac power conversion is made possible without needing a front‐end dc–dc boost converter that improves overall system efficiency, reliability, and power density. However, in most existing SCMLIs, the discharging duration of the rear‐end SCs is much longer than its charging duration, especially when a high number of SC units are adopted. While a high number of level generation is expected to produce a better resolution ac voltage, a significant increase in capacitor's voltage ripple, in contrast, distorts the ac voltage despite using large capacitors. Recently, the switched‐capacitor modular t‐type inverter (SC‐MTI) topology resolved the problem by extending the charging period of all SCs to at least half of the fundamental switching period. However, the high switch count of SC‐MTI introduces a trade‐off in terms of efficiency and cost. In this paper, a new SCMLI topology that retains the good traits of SC‐MTI with switch count reduction is proposed. The merits and feasibility of the proposed SCMLI are verified through simulation and further validated through experimental results for seven‐level considering various operating conditions.

Real time simulation of reduced switch multilevel inverter with PWM switching sequence control

<span lang="EN-US">Reduction of switch count in symmetrical and asymmetrical reduced switch multilevel inverter designs has been proposed regularly with operation of conventional carrier-based pulse width modulation technique. In this study, a novel structure of symmetrical Hexa shaped model reduced switch seven level output inverter is proposed without any auxiliary switch and H-bridge. Proposed structure offers a smaller number of switch count and voltage sources which results in the cost and complexity reduction of its implementation. To operate the switching sequence of inverter from carrier based APOD, POD and PD methods, suitable logical expression to be realize which gained more prominence. Active utilization of two voltage sources in each mode of operation results in significant reduction of voltage stress across each switch is achieved. A comparative study of proposed MLI with various reduced switch MLIs has been presented. Initially, simulation model implementation has been carried out with MATLAB/Simulink and observed the performance parameters and THD. Simulation results are carried for the comparison of the results obtained in the real time work performed on OPAL-RT 5700 simulator</span><span lang="EN-US">.</span>

A three-phase transformer based T-type topology for DSTATCOM application

ABSTRACT Among the various reduced switch count multilevel inverter (RSC-MLI) topologies, T-type is the simplified configuration with appreciable reduction in switch count and, posses an ability to serve an alternative to cascaded H-bridge (CHB) MLI. However, extreme reduction in switch count of T-type topology has limited its switching redundancies and created critical dc-link voltage balancing issues in closed-loop applications. In addition, conventional multi-reference PWM scheme reported for T-type produces poor line-voltage total harmonic distortion (THD). Therefore, in this paper, a five-level T-type topology is presented, which involves only one-third dc source requirement of conventional T-type and CHB. This will greatly reduce the dc-link voltage balancing issues and cost. Further, to improve the harmonic performance of conventional multi-reference PWM, a simple carrier-based modulation scheme is proposed. The open and closed performance on the proposed scheme is validated on Simulink and experimental environment considering five-level T-type configuration. To evaluate the dynamic performance of developed T-type configuration, a three-phase three-wire (3P3W) distributed static compensator (DSTATCOM) application is considered, where its ability to eliminate source current harmonics, reactive power and load unbalance is investigated. To promote the superiority of the developed T-type topology, its cost comparison with conventional T-type and CHB is presented.

A generalized single-phase cascaded multilevel inverter with reduced switch count

The paper presents a new generalized topology-based single-phase cascaded multilevel inverter with reduced power electronic switches, thereby reducing the driver circuits. A new basic unit is proposed in this paper. In order to generate required voltages at the output, an H-bridge is added in conjunction with the basic unit as the unit provides only positive voltage levels. Owing to the merits possessed by cascaded multilevel inverter such as reduction in switch count, driver circuits, low stresses in voltage and their power quality being high, a basic unit is developed. A comparison between the existing topologies and the proposed topology is presented. The developed cascaded 9-level multilevel inverter topology is validated with both simulations and experimentation.

Closed-loop speed control of switched reluctance motor drive fed from novel converter with reduced number of switches

This paper presents a novel converter configuration with fewer for switched reluctance motor (SRM) drive. The proposed novel converter insists for less number of switches compared to conventional asymmetrical type of converter configuration for switched reluctance motor. Switch count reduction in converter reduces the losses, volume of heat sink, and number of gate drive circuits and thereby the performance of the system. Closed loop speed control of switched reluctance motor fed from proposed novel converter topology was presented in this paper. Performance of closed loop operation is compared to open loop system. Further the proposed converter for SRMT is evaluated with loaded condition and comparative analysis of no-load and loaded SRM is presented. The model presented is developed and the results are analyzed using MATLAB/SIMULINK software. Closed loop performance of proposed novel converter fed switched reluctance motor drive is verified at fixed speed and variable speed conditions.

A Novel Architecture of Boost Dc-Link Cascaded Multilevel Inverter for Harmonic Mitigation

Present years have seen the repeated use of the Multi Level Inverters (MLI) with the Photo voltaic (PV) panel in addition more than a few research works have as well been performed in this field. In the past two eras, decreasing the amount of electronic components such as switches, dc sources in MLI are the most important research works. This proposed method principally concentrates on implementing an effective topology with decreased amount of electronic elements for MLI. Reduction in switch count creates the system cost effective. A seven level inverter (+3Vdc, -3Vdc, +2Vdc,-2Vdc and +Vdc, -Vdc and 0) with a single dc source as well as reduced loss in switching power was designed. With the help of multicarrier sinusoidal pulse-width modulation (MCSPWM) method, DC-link switching is attained. It brings about enhanced quality of attained output AC power. Simulation model of a seven-level BDCLCMLI system is designed and to examine its performance for several modulation condition

Grid Interconnecting Solar Generation System Using Transformer Less Cascaded Seven Level Inverter

Multilevel inverter is a power electronic device that is used for high voltage and high power applications and has many advantages like, low switching stress, low total harmonic distortion (THD). Hence, the size and bulkiness of passive filters can be reduced. This paper proposes three topologies of a 7- level cascaded multilevel inverter with reduced number of switches with the 5-level cascaded multilevel inverter and 3-level inverter. The topologies consist of circuits with 9 switches for 7-level CMLI, 8 switches for the 5-level CMLI and 6 switches for the 3-level inverter. Apart from the reduction in switch count this paper also includes minimization of leakage currents and comparative analysis of levels of CMLI’s in every inverter connected to PV source. The control scheme based on Sinusoidal Pulse Width Modulation (SPWM) is adopted due to its ease of implementation. More number of levels results in reduced THD and nearly sinusoidal output. Simulation is performed using Matlab/Simulink.

Three-level NPC Inverter SVM Implementation on Delfino DSC

The aim of the paper is to present implementation of reduced switch count space vector pulse width modulation for three-level neutral point clamped inverters (3L-NPC). The implementation was done using Delfino TMS320F28379D. This dual core digital signal controller (DSC) is used because of compute-intensive nature of implemented modulation. In presented solution the space vector pulse width modulation uses prediction algorithm to reduce the number of individual state changes in power transistors (switch count). This implementation is made because lower number of transistor switching reduces switching losses. The algorithm makes use of additional sets of transistors’ states corresponding to voltages at the output of inverter. Measurements of voltage waveforms and execution time of transistors control algorithm are presented in this paper. Obtained results indicate possibility of further optimization of THD levels and switch count reduction on used DSC.

Single-Stage Switched-Capacitor Module (S3CM) Topology for Cascaded Multilevel Inverter

A two-stage switched-capacitor based multilevel inverter possesses a drawback such that switches in the second stage (i.e., H-bridge) endure higher voltage stress. To resolve this problem, this letter proposes a single-stage switched-capacitor module (S3CM) topology for cascaded multilevel inverter, which ensures the peak inverse voltage across all the switches within the dc source voltage. A total of nine voltage levels can be generated with only one dc source and two incorporated capacitors. Hence, the number of isolated dc sources is significantly reduced compared to a cascaded H-bridge. In addition, voltage boosting gain of two is achieved. A comparative analysis of the recent topology reveals that the proposed S3CM topology achieves switch count reduction. The operation of the proposed topology is validated through circuit analysis followed by simulation and experimental results of a single-module (9-level) prototype.

Reduced carrier PWM scheme with unified logical expressions for reduced switch count multilevel inverters

The significant reduction in switch count of symmetrical/asymmetrical reduced switch count multilevel inverters (RSC-MLI) topologies has modified the operation of inverter such that the conventional carrier-based pulse width modulation (PWM) schemes such as level-shifted PWM and phase-shifted PWM can no more realise them. To control these RSC-MLI topologies, reduced carrier PWM schemes with modified switching logic gained more prominence. These schemes involve suitable logical expressions to realise the switching states of the inverter. However, these logical expressions vary with topological arrangement and number of levels. Moreover, these schemes produce high total harmonic distortion (THD) in line-voltages. Therefore, to improve the line-voltage THD and generalise the switching logic, a modified reduced carrier PWM scheme with unified logical expressions is presented here. The proposed PWM scheme is directly valid for any topology and can be easily scalable to any number of levels in the inverters. To validate the implementation of the proposed PWM to control any RSC-MLI, experimental studies of various asymmetrical RSC-MLI topologies with the proposed PWM scheme are carried out. Further, to verify the superiority of the proposed scheme in terms of THD, complexity, scalability, and computation burden, its performance is compared with carrier-based PWM schemes reported in the literature.

Design and implementation of DC source fed improved dual-output buck-boost converter for agricultural and industrial applications

The proposed research involves, a design and implementation of DC source fed improved Dual output Buck-Boost converter for agricultural and industrial applications. It consists of step up and step-down converter, DC-link module. Compared with conventional two converters, the designed system results in reduction of voltage tension across the switches, compact power switches, DC source reckoning and reduced inrush current. DC-link switching is achieved by reduced ripple voltage which results in improved quality of obtained output power. Reduction in switch count makes the system more cost effective. In addition, the motor speed is regulated by PI controller. Brushless DC Motor produce torque ripple and cause mechanical vibration, acoustic noise due to structural imperfectness and control system, to overcome this suppression control method of vibration for brushless DC motor utilizing feedforward compensation with Fourier transform utilizing a vibration signal acquired by an acceleration sensor attached to the motor frame is proposed. A simulation and prototype model of Dual output Buck-Boost converter is developed, and its performance is analysed for various operating conditions.

An extended dual input dual output three level Z source inverter with improved switch loss reduction technique

Multilevel inverter (MLI) is a proven technology used for industrial applications due to low output total harmonic distortion (THD), high power handling capability and low active device rating. Dual output inverter is a recent trend associated with inverter topologies for specialized applications. This paper deals with three phase three level dual input dual output inverter topology with minimum active device count. Reduction in switch count leads to reduction in losses and improves reliability. Both the input sources share power equally as neutral point current ripple is maintained low. For further reduction in switching losses at higher switching frequencies, the concept of “no switching zone” or discontinuous pulse width modulation (DPWM) has been put forth recently. This paper proposes modification in the placement of “no switching zone” in order to optimize switching losses and output THD (output filtering requirements) for low power factor load. This study also proposes novel graphical approach to analyze the loss reduction along with its effect on output THD. The sinusoidal PWM (SPWM) is used which gives satisfactory switching loss reduction without complex calculations. Moreover, the proposed topology is generalized to provide dual output at higher voltage levels. It is seen that the components reduction phenomenon becomes more pronounced as number of levels goes on increasing. The proposed converter is simulated in MATLAB software environment and results are obtained.

Reduction in number of devices for symmetrical and asymmetrical multilevel inverters

Multilevel inverter (MLI) is receiving remarkable recognition due to its reduced voltage stress across the power switches and low total harmonic distortion in output voltage. However, MLI incorporates large number of semiconductor switches and hence increases its complexity. In this study, new structures of symmetrical and asymmetrical MLI are proposed. The proposed structures offer reduced number of controlled switches, power diodes, capacitors and DC sources as compared with classical and recently proposed topologies in the line. Reduction of switch count, driver circuit and DC voltage sources reduces the size, cost, complexity and enhances overall performance. Moreover significant reduction in voltage stress across the switches can be achieved. A comparative analysis of proposed topologies with the classical topology and recently published topologies has been made in terms of controlled switches, power diodes, driver circuit requirement, DC voltage sources and blocking voltage. Multi-carrier pulse width modulation strategy is adopted for generating the switching pulses. The detailed simulation study of the proposed topology has been carried out using MATLAB/Simulink and feasibility of topology has been validated experimentally.

Hybrid topology of symmetrical multilevel inverter using less number of devices

The interest in development of newer topologies of multilevel inverter has been increasing rapidly in past few years. Recently introduced topologies achieve higher number of output voltage steps with reduced number of switches, DC voltage sources, voltage stress across switches and losses as compared with the conventional topologies. In this study, a new structure of symmetrical multilevel inverter is proposed. The proposed structure offers reduced number of controlled switches, power diodes and DC sources as compared with classical and recently proposed topologies in the literature. Reduction of switch count and DC voltage sources reduces the size, cost, complexity and enhances overall performance. Proposed topology is capable of producing 7, 9 and 11 levels of output voltage with seven switches only. Moreover, significant reduction in voltage stress across the switches can be achieved. A comparative analysis of proposed topology with the conventional topology and recently published topologies has been made in terms of controlled switches, power diodes, driver circuit requirement, DC voltage sources and blocking voltage. Multi-carrier pulse-width modulation strategy is adopted for generating the switching pulses. Simulation study of the proposed topology has been carried out using Matlab/Simulink and feasibility of topology has been validated experimentally.

Comparison of power losses, current and voltage stresses of semiconductors in voltage source transformerless multilevel inverters

The power losses, current and voltage stresses in semiconductor devices in voltage source transformerless multilevel inverters (VSTMLIs) topologies are unequal, depending on the switching states, the duty ratio, the levels of output voltage, the load power factor and the depth of modulation index. Non-uniform power loss profiles mean both unequal junction temperature and power rating in semiconductors. In this study, a comparison of power losses, current and voltage stresses in semiconductors of VSTMLIs is performed. Initially, the structural characteristics and operating principles of dominant VSTMLIs with sinusoidal pulse width modulation are analysed. Then, modifications of existing VSTMLIs and simplified multilevel topologies are proposed, which achieve a further reduction in switch count and power losses in semiconductors. The proposed modified circuitries are suitable for converting existing four-level VSTMLI topologies into five-level ones. This conversion is desirable, when a zero output voltage level under no-load conditions or low modulation indices should be obtained. Power losses in semiconductors are calculated analytically and then confirmed by simulation. A comparative presentation of profiles of power losses, current and voltage stresses in semiconductors of the examined VSTMLIs is analytically carried out. The obtained results are valuable for sizing and selecting the semiconductors in VSTMLIs.

Design and Evaluation of PI Controller for Four Switch BLDC Motor Drive

This article presents a comprehensive study on implementing four switch brushless DC (BLDC) motor drive for variable speed applications with PI controller. In this system, four switches are used in the commutation circuit to lower cost and improve performance. The reduction in the number of power semiconductor switches leads to reduction of losses and the control circuit. The principle of operation, switching sequence formulation for the four switch BLDC motor drive is presented. A PI controller is designed for speed control and evaluated by simulation for performance under various speed and load conditions. The designed closed loop controlled BLDC motor drive shows satisfying performance despite the reduction of switch count. The steady state error of the system is limited within 1% while improving the transient performance.