Three-level NPC Inverter SVM Implementation on Delfino DSC

Abstract

The aim of the paper is to present implementation of reduced switch count space vector pulse width modulation for three-level neutral point clamped inverters (3L-NPC). The implementation was done using Delfino TMS320F28379D. This dual core digital signal controller (DSC) is used because of compute-intensive nature of implemented modulation. In presented solution the space vector pulse width modulation uses prediction algorithm to reduce the number of individual state changes in power transistors (switch count). This implementation is made because lower number of transistor switching reduces switching losses. The algorithm makes use of additional sets of transistors’ states corresponding to voltages at the output of inverter. Measurements of voltage waveforms and execution time of transistors control algorithm are presented in this paper. Obtained results indicate possibility of further optimization of THD levels and switch count reduction on used DSC.