Reduction Of Static Power Consumption Research Articles

SPONGE+: A NoC-based power gating scheme for overall router column opening and closing control

Power gating, a general-purpose power saving technique, can be used to turn off inactive routers in Networks-on-Chip (NoCs) to reduce static power consumption. SPONGE is an advanced power gating scheme. When the router is dormant, SPONGE maintains the transmission of straight packets, which occupy a large percentage of the network, through a direct bypass design. At the same time, the energized router column’s can ensure the normal transmission of turning packets. However, it suffers from increased latency due to excessive detours, aggravated load imbalance, and violation of the breakeven time (BET) constraint. To address the above problems, we propose an improved energy-efficient router architecture SPONGE+. First, we design a new router bypass architecture that enables powered-off routers to have the ability to transmit straight ahead and turn in the X-to-Y direction to reduce the bypass cost of packet transmission. Secondly, we propose a congestion-aware turning routing algorithm to balance the load among powered-on routers and improve network resource utilization. Finally, we pin improves the power gating mechanism for router columns to satisfy the BET constraint and further reduce the static power expenses. Experimental results indicate that, under real application scenarios, our scheme achieves a 27.3% reduction in static power consumption and a 10.5% decrease in packet latency compared to SPONGE, with commendable scalability.

A novel CNTFET based Schmitt-Trigger read decoupled 12T SRAM cell with high speed, low power, and high [formula omitted]/[formula omitted] ratio

Many researchers are working to develop a static random access memory (SRAM) cell that uses low power, has good stability, better Ion/Ioff ratio and speed. This paper presents a single sided Schmitt-trigger driven read decoupled 12 transistors (STRD 12T) carbon nanotube field-effect transistor (CNTFET) SRAM cell with controlled power gating approach. The Schmitt-trigger (ST) inverter along with power gating and read decouple approach has low power, good read and write delay, better stability and Ion/Ioff ratio. The stacking effect reduces the leakage power of the proposed cell. The proposed STRD 12T SRAM illustrates the maximum reduction in static power consumption, write delay, read delay, and maximum improvement in Ion/Ioff ratio is 1544.34, 112.37, 1.40, and 8107.88 times respectively, than the considered SRAM cells. The simulation is performed with Cadence Virtuoso utilizing the 32 nm CNTFET model from Stanford University.

Energy efficient parallel hybrid adder architecture for 3X generation in radix-8 booth encoding

The need for hard (3X) multiple generation in radix-8 booth encoding increases the complexity of partial product generation and the latency of the multiplier. The source of delay is primarily the propagation of carry signals. A variety of carry propagate adder architectures have been studied to overcome this drawback. In this paper, we propose a hybrid adder architecture that precomputes the simultaneous generation of pseudo carry signals by exploiting the symmetry of 3X multiple and the final carry generation using Ling prefix network. As the Ling adder in the carry path reduces the complexity, the proposed adder results in significant improvement in the power delay product ($${\sim }$$25–55%) compared to state of the art 64 bit adders. This adder decreases the number of logic gates in the critical path, leading to a reduction in static power consumption. As a design metric, it is necessary to minimize the energy dissipation of logic modules, the results indicate that the proposed hybrid adder would fulfil the requirements of processors in deep sub-micron VLSI technology.

Dual-Metal-Gate InAs Tunnel FET With Enhanced Turn-On Steepness and High On-Current

A novel approach to optimize tunnel field-effect transistors (TFETs) by technology computer-aided design simulations is reported. The most interesting outcome of our design effort is a dual-metal-gate (DMG) TFET, which features an inverse subthreshold slope (SS) significantly over more than five orders of magnitude of drain current, with a minimum value of 6 mV/decade sustained across one drain-current decade or more. The DMG-TFET simultaneously fulfills both the low-standby-power off-state current and the high-performance on-state current at a supply voltage of 0.5 V. Therefore, 25% reduction of static power consumption is expected compared with the 2020 International Technology Roadmap for Semiconductors requirements for multigate transistors.