Power Supply Noise Reduction Research Articles

Frequency- and Time-Domain Yield Optimization of a Power Delivery Network Subject to Large Decoupling Capacitor Tolerances

Suboptimal design of power delivery networks (PDNs) may cause performance deterioration and severe functional failures on high-speed computer platforms. Voltage regulators (VRs) distribute controlled voltage in the PDN to the active devices, providing a steady power supply at a desired DC voltage level with an acceptable noise level or ripple. Unacceptable voltage drops can be caused by transient switching currents at the devices. Many decoupling capacitors are commonly used to lower the PDN impedance profile in order to reduce power supply noise and to supply fast transient current to switching devices. However, commercially available decoupling capacitors typically present large manufacturing variability. In this article, we first propose an optimization methodology that gradually finds the best compensation parameter values of a buck converter VR to meet suitable stability criteria. Simultaneously, the number of parallel decoupling capacitors in the PDN is minimized while meeting a frequency-domain impedance profile specification and a time-domain minimum voltage droop requirement under nominal parameter values. Finally, a statistical analysis, yield estimation, and yield optimization of the nominally optimized PDN subject to large decoupling capacitor tolerances is presented. We consider the impedance profile, transient voltage droop, and VR stability as the responses of interest for yield calculation.

A low-noise and fast transient response LDO design for high-speed SerDes

In order to deal with the special needs of high-speed digital-analog hybrid circuits for power supplies, this article has designed a LDO circuit specifically applied to high-speed SerDes. In the design process, a cross-coupled charge pump was used to increase the swing and reduce power supply noise, and to increase the gain and reduce the area overhead, the design of an asymmetric operational amplifier was introduced. At the same time, the use of the cascode structure is also conducive to the frequency stability of the loop and provides sufficient phase margin for the circuit. Through simulation verification, the low-frequency maximum internal noise of this LDO is only 0.96uV/sqrt(Hz), the transient response time when the load changes from low to high is 38ns, the transient response time from high to low is 84ns, the phase margin is 87.3deg, and the PSRR is 56.8dB.

A CAD approach for power supply noise aware floorplan in SoC

This paper deals for reduction of power supply noise with decoupling capacitor estimation and allocation using particle swarm optimisation (PSO) algorithm at the floorplanning stage of the physical...

Beol Compatible High-Capacitance Mimcap Structure Using ZrO2 with Enhanced Dielectric Constant

We demonstrate a MIM capacitor structure using ZrO2 for the dielectric layer which exhibits a 25% capacitance increase (from ~43fF/mm2 to >55fF/mm2 for a ~55 Å film) with minimal leakage current increase compared to Hf based dielectrics, extending the usefulness of MIM on-chip decoupling capacitors. The MIM structure, suitable for BEOL processing is TiN/ZrO2/TiN combined with an anneal which is shown to improve the capacitance vs. leakage performance compared to doped and undoped HfO2 based control structures. GI-XRD measurements demonstrate that the capacitance increase corresponds with a phase transformation of the ZrO2 from amorphous to cubic phase, which is shown to have a dielectric constant (k) up to 35. Reliability models based on hard-breakdown (HBD) show that this structure exceeds the end-of-life targets.Servers and high-performance chips have historically relied on on-chip decoupling capacitors (decap) to reduce power supply noise in order to achieve 3 – 5.4 GHz operating frequency. Although packaging decap can be very effective at mitigating low and mid-frequency noise, on-chip decap, such as MIMCAP, is critical for mitigating mid and high-frequency noise. As Fig. 1 shows, an increase in on-chip decap can result in a significant performance benefit, due to their fast response time slowing the fastest droops, giving time for slower response elements to contribute. One method of achieving this increased decap is to increase the k of the material being used as the insulator in the MIMCAP. Following high-k gate dielectric technology, HfO2 and other Hf based dielectric stacks have been used for this layer successfully [1]. But there is a significant difference in the thermal budget that the dielectric is exposed to following the deposition between gate dielectric and MIMCAP applications. The gate dielectric, deposited prior to any metallization, will typically be exposed to a relatively high thermal budget compared to the insulator layer of a decoupling MIMCAP, which is usually placed between wiring levels in the back end of the line (BEOL) [2]. Since the thermal budget after deposition will affect the crystal structure of a material, and different crystal phases of the same material can have dramatically different dielectric constants [3], the actual dielectric constant of a particular high-k material may vary significantly depending on whether it is used as the gate dielectric or as the MIM insulator. In this work, we explore the use of a ZrO2 as the high- k layer for MIMCAP applications and show that its low crystallization temperature enables it to achieve a significantly higher k value compared to HfO2 when processed under BEOL compatible thermal conditions.Fig. 2 shows the development of the high-k phase of a 55 Å ZrO2 film as the anneal temperature is increased. The peaks at 35°, 42° and 52° are the signature of the bottom TiN electrode and do not change with anneals; but the peaks at 30.2° and 50.3° , which are seen to develop as the anneal temperature increases, match with the 111 and 220 planes of the cubic phase of ZrO2. MIMCAPs built using similarly annealed ZrO2 layers as dielectrics exhibit an increase in capacitance as shown in Fig. 3a: there is a slight increase after anneal A, significantly more increase after anneal B, and additional moderate increases after C and D. No such capacitance increase is seen when Hf based dielectrics are used (Fig. 3b). The maximum capacitance is found to be ~56fF/um2 after anneal D compared to ~43fF/um2 for the unannealed device, an increase of more than 25%, while the leakage current remains virtually unchanged at 1V, and increases by <5x at 2V. Fig. 3c graphs the calculated value of k as a function of the thermal budget, confirming that the ZrO2 layer has the property of crystallizing to its high- k phase at temperatures relatively lower than is typical for HfO2. Thus, we can achieve high capacitance with a relatively thick high-k layer, keeping the leakage current low, all while maintaining compatibility with BEOL processing.[1] T. Ando et al., “CMOS Compatible MIM Decoupling Capacitor with Reliable Sub-nm EOT High-k Stacks for the 7nm Node and Beyond,” Tech. Dig. IEDM 2016, pp. 9.4.1 - 9.4.4.[2] K. Fischer et al., “Low-k Interconnect Stack with multi-layer Air Gap and Tri-Metal-Insulator-Metal Capacitors for 14-nm High Volume Manufacturing,” IEEE Interconnect Tech. Conf. 2015, 10.1109/IITC-MAM.2015.7325600.[3] X. Zhao and D. Vanderbilt, “First-principles Study of Electronic and Dielectric Properties of ZrO2 and HfO2” MRS Proceedings, 747. doi:10.1557/PROC-747-T5.2/N7.2. Figure 1

Soft Computing Techniques Based CAD Approach for Power Supply Noise Reduction in System-on-Chip

Implementation of efficient power distribution network is a challenging task in modern day system-on-chip. During switching of transistors the signal integrity problems arises, such as, resistive drop, inductive noise and electro-migration, causing voltage fluctuations known as supply noise. This supply noise may result in malfunctioning of the integrated circuit. Insertion of decoupling capacitance is a commonly used technique for suppression of supply noise. In this article flower pollination algorithm has been used to estimate the decoupling capacitor budget to reduce power supply noise. Another major issue is allocation of decoupling capacitors in the floorplan of the design. To get the best possible results in the post-layout stage particle swarm optimization algorithm has been used in the floorplan stage. The purpose of this work is to reduce the supply noise without having much effect on the other design parameters of the chip. Simulation results show that noise voltage has been reduced significantly without much effecting other design parameters. This approach can be used in any system-on-chip.

BEOL Compatible High-Capacitance MIMCAP Structure Using a Novel High k Material

We demonstrate a MIM capacitor structure using ZrO2 for the dielectric layer which exhibits a 25% capacitance increase (from ~43fF/mm2 to >55fF/mm2 for a ~55A film) with minimal leakage current increase compared to Hf based dielectrics, extending the usefulness of MIM on-chip decoupling capacitors. The MIM structure, suitable for BEOL processing is TiN/ZrO2/TiN combined with an anneal which is shown to improve the capacitance vs. leakage performance compared to doped and undoped HfO2 based control structures. GI-XRD measurements demonstrate that the capacitance increase corresponds with a phase transformation of the ZrO2 from amorphous to cubic phase, which is shown to have a dielectric constant (k) up to 35. Reliability models based on hard-breakdown (HBD) show that this structure exceeds the end-of-life targets.Servers and high-performance chips have historically relied on on-chip decoupling capacitors (decap) to reduce power supply noise in order to achieve 3 – 5.4 GHz operating frequency. Although packaging decap can be very effective at mitigating low and mid-frequency noise, on-chip decap, such as MIMCAP, is critical for mitigating mid and high-frequency noise. As Fig. 1 shows, an increase in on-chip decap can result in a significant performance benefit, due to their fast response time slowing the fastest droops, giving time for slower response elements to contribute. One method of achieving this increased decap is to increase the k of the material being used as the insulator in the MIMCAP. Following high-k gate dielectric technology, HfO2 and other Hf based dielectric stacks have been used for this layer successfully [1]. But there is a significant difference in the thermal budget that the dielectric is exposed to following the deposition between gate dielectric and MIMCAP applications. The gate dielectric, deposited prior to any metallization, will typically be exposed to a relatively high thermal budget compared to the insulator layer of a decoupling MIMCAP, which is usually placed between wiring levels in the back end of the line (BEOL) [2]. Since the thermal budget after deposition will affect the crystal structure of a material, and different crystal phases of the same material can have dramatically different dielectric constants [3], the actual dielectric constant of a particular high-k material may vary significantly depending on whether it is used as the gate dielectric or as the MIM insulator. In this work, we explore the use of a ZrO2 as the high- k layer for MIMCAP applications and show that its low crystallization temperature enables it to achieve a significantly higher k value compared to HfO2 when processed under BEOL compatible thermal conditions.Fig. 2 shows the development of the high-k phase of a 55A ZrO2 film as the anneal temperature is increased. The peaks at 35, 42 and 52 are the signature of the bottom TiN electrode and do not change with anneals; but the peaks at 30.2 and 50.3 degrees, which are seen to develop as the anneal temperature increases, match with the 111 and 220 planes of the cubic phase of ZrO2. MIMCAPs built using similarly annealed ZrO2 layers as dielectrics exhibit an increase in capacitance as shown in Fig. 3a: there is a slight increase after anneal A, significantly more increase after anneal B, and additional moderate increases after C and D. No such capacitance increase is seen when Hf based dielectrics are used (Fig. 3b). The maximum capacitance is found to be ~56fF/um2 after anneal D compared to ~43fF/um2 for the unannealed device, an increase of more than 25%, while the leakage current remains virtually unchanged at 1V, and increases by <5x at 2V. Fig. 3c graphs the calculated value of k as a function of the thermal budget, confirming that the ZrO2 layer has the property of crystallizing to its high- k phase at temperatures relatively lower than is typical for HfO2. Thus, we can achieve high capacitance with a relatively thick high-k layer, keeping the leakage current low, all while maintaining compatibility with BEOL processing.[1] T. Ando et al., “CMOS Compatible MIM Decoupling Capacitor with Reliable Sub-nm EOT High-k Stacks for the 7nm Node and Beyond,” Tech. Dig. IEDM 2016, pp. 9.4.1 - 9.4.4.[2] K. Fischer et al., “Low-k Interconnect Stack with multi-layer Air Gap and Tri-Metal-Insulator-Metal Capacitors for 14-nm High Volume Manufacturing,” IEEE Interconnect Tech. Conf. 2015, 10.1109/IITC-MAM.2015.7325600.[3] X. Zhao and D. Vanderbilt, “First-principles Study of Electronic and Dielectric Properties of ZrO2 and HfO2” MRS Proceedings, 747. doi:10.1557/PROC-747-T5.2/N7.2. Figure 1

Low Dropout Based Noise Minimization of Active Mode Power Gated Circuit

Power gating technique reduces leakage power in the circuit. However, power gating leads to large voltage fluctuation on the power rail during power gating mode to active mode due to the package inductance in the Printed Circuit Board. This voltage fluctuation may cause unwanted transitions in neighboring circuits. In this work, a power gating architecture is developed for minimizing power in active mode and noise is analyzed. The effect of different noise minimization approaches for reducing power supply noise is evaluated in power gating architecture. A new concept of noise minimization technique using Low Dropout Voltage regulator is proposed in this paper. The amount of charge in the internal nodes of the power gating circuit passes through the sleep transistors during the wake-up transition is controlled by the proposed noise minimization techniques. The Low Dropout Voltage Regulator is designed newly in such a way that can be used to reduce bounce noise by minimizing voltage fluctuation on the power rail of power gating circuit. Architectures have been developed in Synopsys Custom Designer tool at iPDK 90nm technology. Percentage saving of noise on the power supply is reduced up to 99%.

Power Supply Noise Reduction of Multicore CPU by Staggering Current and Variable Clock Frequency

Central processing unit (CPU) for any computer generally operates at constant power supply voltage. Normally in product specification, this power supply voltage has tolerance margin close to ±5%. It is shown in the previous works that for every millivolt drop in power supply voltage, the operation frequency of a chip reduces by about 2 MHz. This voltage drop occurs when CPU starts drawing current from the power supply. It is desirable to maintain the supply voltage within the specification of allowed voltage fluctuations so that the CPU can run at the target operating frequency, for a given package inductance and die decoupling capacitance. In this paper, power supply noise reduction method for multicore CPU in a given silicon chip has been considered. The concept of variable frequency has been applied on every core to minimize the noise by changing the current ramp of a multicore system. This reduces the dI/dt, and therefore for fixed package inductance and die decoupling capacitance, the power supply noise reduces. In this paper, four-core CPU has been taken and also shown the reduction of noise by changing the current ramp using variable clock frequency on each core and also by staggering the time when each core will start clocking.

Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction

This paper proposes a triangular active charge injection method to reduce resonant power supply noise by injecting the adequate amount of charge into the supply line of the LSI in response to the current consumption of the core circuit. The proposed circuit is composed of three key components, a voltage drop detector, an injection controller circuit and a canceling capacitor circuit. In addition to the theoretical analysis of the proposed method, the measurement results indicate that our proposed method with active capacitor can realize about 14% noise reduction compared with the original noise amplitude. The proposed circuit consumes 25.2 mW in steady state and occupies 0.182 mm2.

A novel Li-ion battery charger using multi-mode LDO configuration based on 350 nm HV-CMOS

The design of a novel Li-ion battery charger using multi-mode LDO architecture has been introduced in this paper. The proposed architecture, using an improved multi-mode LDO, not only obtains high accuracy but also reduces power supply noise because of utilizing novel error amplifier and power buffer configuration; while still consuming low power dissipation. To obtain the low power consumption, the Schmitt Trigger technique is applied to the charging controller and an optimized current driven circuit is proposed. Besides, the PSRR parameter is also enhanced by adding pre-regulation circuit in multi-mode LDO circuit. Thus, the proposed Li-ion battery charger achieves 700 mA operation current with 70.9 % efficiency but only dissipates 495 mW in power. During the charging process, the setting time and ripple issues are solved by the use of soft-start circuit which is integrated into the charging controller in order to decrease the chip area. Therefore, the setting time is reduced to 5.5 μs while gaining the load regulation at approximately 0.019 μV/mA and increasing PSRR up to 106 dB at DC level. Moreover, the line regulation is also reduced at 1.3 mV/V. The proposed linear battery charger is designed and implemented, based on High-Voltage CMOS process with using 4.5 V power supply voltage and obtaining 4.2 V battery output voltage.

A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOS

In this paper, a data-jitter mixing (DJM) forwarded-clock receiver is proposed that achieves high jitter correlation between data and a clock for high speed and small power consumption. The first-stage injection-locked oscillator (ILO) filters out high-frequency clock jitter that loses the correlation due to a latency mismatch between data and the clock. Then, a data-jitter mixer in the second stage of the proposed receiver further increases the jitter correlation reduced by nonoptimal jitter filtering in ILO. Moreover, the DJM reduces power supply noise induced jitter from a clock distribution network, while the conventional jitter filter cannot track the high-frequency jitter because of filtering it out. A prototype receiver implemented in 1-V 65-nm CMOS process achieves 9.6 Gb/s with 1.22-mW/Gb/s in spite of a 1.92-ns latency mismatch between data and a clock.

Mixing Drivers in Clock-Tree for Power Supply Noise Reduction

In today's process technologies, power supply noise may cause serious clock jitter and circuit malfunction. Noise occurs by the fast and simultaneous voltage switching. A primary contributor to the noise is the clock-tree and the underlying sequential circuits that switch simultaneously, thus causing high current peaks. This work proposes to spread the switching of the clock-tree drivers, while maintaining low skew at the sinks of the tree, where the clocked circuits are connected. Driver switching characterization has been used for fast computation of peak currents, delays and slopes, integrated in a two-phase algorithm. It first constructs the clock-tree in a top-down traversal, employing a mix of high threshold voltage (HVT) and weak low threshold voltage (LVT) clock-drivers. A bottom-up delay correction phase then takes place, aiming at clock skew minimization. The algorithm was implemented in 40 nanometers TSMC process technology, achieving 35% to 70% clock-tree peak current reduction, translated to similar reduction in power supply noise. The proposed method can easily be combined with other existing methods to further reduce the noise.

Resonant Power Supply Noise Reduction by STO Capacitors Fabricated on Interposer

This paper demonstrates the resonant power supply noise reduction effects of STO thin film decoupling capacitors, which are embedded in interposers. The on-interposer STO capacitor consists of SrTiO2 whose dielectric constant is about 20 and is sandwitched by Cu films in an interposer. The on-interposer STO capacitors are directly connected to the LSI PADs so that they provide large decoupling capacitance without package leadframe/bonding wire inductance, resulting in the reduction of the resonant power supply noise. The measured power supply waveforms show significant reduction of the power supply noise, and the Shmoo plots also show the contribution of the STO capacitors to the robust operations of LSIs.

Power Delivery for 3-D Chip Stacks: Physical Modeling and Design Implication

3-D integration creates vast opportunities to improve performance and the level of integration in nanoelectronic systems. However, 3-D integration presents many challenges for power delivery network design due to larger supply currents and longer power delivery paths compared to 2-D systems. In this paper, an analytical physical model is derived to incorporate the impact of 3-D integration on power supply noise. The model has less than 4% error compared to SPICE simulations. Based on the model, design guidelines and opportunities for reducing power supply noise, such as inserting “decap” die and through-vias, are discussed in this paper.

Skewing-based method for reduction of functional crosstalk and power supply noise caused by on-chip buses

In this study, the authors present an optimisation method based on analytical resistance, inductance and capacitance (RLC) models for simultaneous reduction of both functional crosstalk noise and power supply noise caused by on-chip buses. This is achieved by intentional skewing of the relative timing of adjacent wires. The method is applicable to any number of bus wires and it takes into account both capacitive and inductive coupling between wires. The authors model the effect of skewing on both functional crosstalk in a distributed RLC bus and the power noise in the surrounding RLC power distribution network. The model is verified by comparing it with HSPICE in 65 nm technology, with the average error being 1.4%. The capability of the method in reducing problematic long-range inductive crosstalk noise is demonstrated in a case study where the maximum crosstalk noise is reduced from 0.20 to 0.05 V. Implementation and the use of the method in combination with other crosstalk reduction methods and power supply noise reduction methods are presented. The influence of the number of different skewing times is analysed.

Electret microphone buffer circuit with significantly enhanced power supply rejection

A microphone buffer circuit being adaptable for connection to a power source is disclosed. The microphone buffer circuit includes an input transistor operably connected between an input and an output for buffering an input signal. The microphone buffer circuit includes a means for reducing power supply noise capable of being coupled to the input transistor wherein the means being operably connected to the input transistor and the power source.

Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment

Yield loss caused by excessive power supply noise has become a serious problem in at-speed scan testing. Although X-filling techniques are available to reduce the launch cycle switching activity, their performance may not be satisfactory in the linear-decompressor-based test compression environment. This paper solves this problem by proposing a novel integrated automatic test pattern generation scheme that efficiently and effectively performs compressible low-capture-power X -filling. Related theoretical principles are established, based on which the problem size is substantially reduced. The proposed scheme is validated by benchmark circuits, as well as an industry design in the embedded deterministic test environment.

Data Bus Inversion in High-Speed Memory Applications

Efforts to reduce high-speed memory interface power have led to the adoption of data bus inversion or bus-invert coding. This study compares two popular algorithms, which seek to limit the number of simultaneously transitioning signals and bias the state of transmitted data toward a preferred binary level, respectively. A new algorithm, which provides a compromise between transition frequency and preferred signal level, is proposed, and the three algorithms are compared in terms of their impact on power consumption, power supply noise reduction, and general signal integrity enhancement when used in conjunction with a variety of link topologies.

Clock Scheduling and Cell Library Information Utilization for Power Supply Noise Reduction

Power supply noise is fundamentally caused by large current peaks. Since large current peaks are induced by simultaneous switching of many circuit elements, power supply noise can be minimized by deliberate clock scheduling which utilizes nonzero clock skew. In this paper, nonzero skew clock scheduling is used to avoid the large peak current and consequently reduce power supply noise. While previous approaches require extra characterization efforts to acquire current waveform of a circuit, we approximate it only with existing cell library information to be easily adapted to conventional design flow. A simulated annealing based algorithm is performed, and the peak current values are estimated for feasible clock schedules found by the algorithm. The clock schedule with the minimum peak current is selected for a solution. Experimental results on ISCAS89 benchmark circuits show that the proposed method can effectively reduce the peak current.

An Improved Active Decoupling Capacitor for “Hot-Spot” Supply Noise Reduction in ASIC Designs

On-chip decoupling capacitors (decaps) are widely used to reduce power supply noise by placing them at the appropriate locations on the chip between blocks. While passive decaps can provide a certain degree of protection against IR drop, if a problem is found after the physical design is completed, it is difficult to implement a quick fix to the problem. In this paper, we investigate the use of an active decap as a drop-in replacement for passive decaps to provide noise reduction for these so-called ldquohot-spotrdquo IR drop problems found late in the design process. A modified active decap design is proposed for ASIC applications operating up to 1 GHz. Our improvement uses latch-based comparators as the sensing circuit, which provides a better power/delay tradeoff than previous designs and incorporates hysteresis to minimize unnecessary switching. It is implemented in a 1 V-core 90 nm CMOS process with a total area of 0.085 mm2 and static power of 2.8 mW. Measurements from a number of test chips show that using an active decap can provide between 10%-20% noise reduction in the 200 MHz-1 GHz frequency range over its passive counterpart. Sizing and placement analyses are also carried out using circuit simulation. The active decap is most effective when placed in close proximity to the hot-spot, as compared to the passive decap which is less sensitive to the exact location. Overall, if sized and placed properly, active decaps can provide an additional 20% reduction in supply noise over passive decaps.