Soft Computing Techniques Based CAD Approach for Power Supply Noise Reduction in System-on-Chip

Abstract

Implementation of efficient power distribution network is a challenging task in modern day system-on-chip. During switching of transistors the signal integrity problems arises, such as, resistive drop, inductive noise and electro-migration, causing voltage fluctuations known as supply noise. This supply noise may result in malfunctioning of the integrated circuit. Insertion of decoupling capacitance is a commonly used technique for suppression of supply noise. In this article flower pollination algorithm has been used to estimate the decoupling capacitor budget to reduce power supply noise. Another major issue is allocation of decoupling capacitors in the floorplan of the design. To get the best possible results in the post-layout stage particle swarm optimization algorithm has been used in the floorplan stage. The purpose of this work is to reduce the supply noise without having much effect on the other design parameters of the chip. Simulation results show that noise voltage has been reduced significantly without much effecting other design parameters. This approach can be used in any system-on-chip.