Leakage Current Reduction Research Articles

Single phase transformerless inverter topology with reduced leakage current for grid connected photovoltaic system

Leakage current is the main concern of the grid connected transformerless photovoltaic (PV) inverters. Many single phase transformerless inverter topologies with reduced leakage current have been introduced in the past few years. These are mainly classified on the basis of leakage current reduction methods Galvanic isolation without- common mode voltage (CMV) clamping and with-CMV clamping. It has been shown that leakage current generation is highly dependent on CMV. CMV of the topologies without- CMV clamping oscillates and oscillation amplitude depends on switches’ junction capacitances and parasitic parameters of the topology. In order to eliminate the leakage current completely, CMV must be constant throughout the inverter operation. Moreover, inverter should also be capable to inject definite amount of reactive power into the grid, as demanded by the international regulations. In this study, reduced leakage current CMV clamped topology is proposed which can eliminate leakage current and capable of injecting reactive power into the grid. Total harmonic distortions (THD) of injected grid current at various solar irradiance levels are also analyzed. In order to verify the theoretical explanations, the proposed topologies are simulated in Matlab/Simulink environment. Finally, the simulated results are validated experimentally.

GaN Lateral High Voltage Photoconductive Semiconductor Switches

Wide bandgap GaN photoconductive semiconductor switches (PCSSs) have gained recent attention due to high critical electric field strength and high electron saturation velocity to provide high power ultrafast devices. To reduce leakage currents, PCSSs have previously been demonstrated on semi-insulating GaN achieved by Fe compensation doping. However, Fe is known to have strong memory effects, which can redistribute Fe into subsequent films, as well as a narrow window of acceptable doping levels. PCSSs with fast response time are required for applications requiring high repetition rates. C-doped GaN is used to reduce leakage current and improve the photocurrent of lateral PCSSs. The C-doping is performed by simply tuning the growth parameters, such as temperature, pressure and III/V ratio and creates shallow accepter levels, compensating any unintentional n-type doping. In this work, we demonstrate high voltage GaN:C PCSSs with fast response times measured using a picosecond pulsed laser and high breakdown voltages, over 4000 V, measured in a vacuum probe station.

Electrically driven, highly efficient three-dimensional GaN-based light emitting diodes fabricated by self-aligned twofold epitaxial lateral overgrowth

Improvements in the overall efficiency and significant reduction in the efficiency droop are observed in three-dimensional (3D) GaN truncated pyramid structures fabricated with air void and a SiO2 layer. This 3D structure was fabricated using a self-aligned twofold epitaxial lateral overgrowth technique, which improved both the internal quantum efficiency and the light extraction efficiency. In addition, a reduced leakage current was observed due to the effective suppression of threading dislocations. While this study focuses primarily on the blue emission wavelength region, this approach can also be applied to overcome the efficiency degradation problem in the ultraviolet, green, and red emission regions.

Analysis and design of lector-based dual-Vt domino logic with reduced leakage current

PurposeThis paper aims to propose a new lector-based domino and examine it with inputs and clock signal combination in a 45-nm dual-threshold footerless domino circuit for reduced leakage current.Design/methodology/approachIn this technique, p-type and n-type leakage control transistors (LCTs) are introduced between pull-up and pull-down networks, and the gate of one is controlled by the source of the other. A high-threshold transistor is used in the input for reducing gate oxide leakage current, which becomes dominant in nanometre technology. Simulations were based on a 45-nm BISM 4 model using an HSPICE simulator for proposed domino circuits.FindingsThe result shows that CHIL (clock high and input low) state is ineffective for lowering leakage current and the conventional CHIH (clock high and input high) state is only effective to suppress the leakage at low temperature for wide fan-in domino circuits. At high temperature, CLIL (clock low and input low) state is preferable to reduce the leakage current for low fan-in domino, but for high fan-in domino, CHIH state is preferred. The proposed circuit technique for AND2, OR2, OR4 and OR8 circuits reduces the active power consumption by 50.94 to 75.68 per cent and by 64.85 to 86.57 per cent at low and high die temperatures, respectively, when compared to the standard dual-threshold voltage domino logic circuits.Originality/valueThe research proposes a new leakage reduction technique used in domino circuits and also evaluates the state for leakage reduction which can be used for low-power dynamic circuits.

HfSe2 and ZrSe2: Two-dimensional semiconductors with native high-κ oxides.

The success of silicon as a dominant semiconductor technology has been enabled by its moderate band gap (1.1 eV), permitting low-voltage operation at reduced leakage current, and the existence of SiO2 as a high-quality "native" insulator. In contrast, other mainstream semiconductors lack stable oxides and must rely on deposited insulators, presenting numerous compatibility challenges. We demonstrate that layered two-dimensional (2D) semiconductors HfSe2 and ZrSe2 have band gaps of 0.9 to 1.2 eV (bulk to monolayer) and technologically desirable "high-κ" native dielectrics HfO2 and ZrO2, respectively. We use spectroscopic and computational studies to elucidate their electronic band structure and then fabricate air-stable transistors down to three-layer thickness with careful processing and dielectric encapsulation. Electronic measurements reveal promising performance (on/off ratio > 106; on current, ~30 μA/μm), with native oxides reducing the effects of interfacial traps. These are the first 2D materials to demonstrate technologically relevant properties of silicon, in addition to unique compatibility with high-κ dielectrics, and scaling benefits from their atomically thin nature.

Fabrication and Characterization of Graphene-on-Silicon Schottky Diode for Advanced Power Electronic Design

In this study, graphene-on-silicon process technology was developed to fabricate a power rectifier Schottky diode for efficiency improvement in high operating temperature. Trench-MOS-Barrier-Schottky (TMBS) diode structure was used to enhance the device performance. The main objective of this research was to study the effect of reduced graphene oxide (RGO) deposited on silicon surface for Schottky barrier formation and heat transfer in Schottky junction. The study showed RGO deposited on silicon as a heat spreader could help to reduce the effect of heat generated in the Schottky junction that leads to a leakage current reduction and efficiency improvement in the device. With comparison to the conventional metal silicide (titanium silicide and cobalt silicide), the leakage reduced by two-orders of magnitude when tested under high operating temperature (>100°C). TMBS rectifier diode that uses graphene-based heat spreader could produce highly reliable product able to withstand high temperature operating condition.

Single-event-transient effects in Junctionless Double-Gate MOSFETs with Dual-Material Gate investigated by 3D simulation

The Junctionless Double-Gate MOSFET combined with a Dual-Material Gate (JL-DMDG) is interesting for future ultra-scaled devices thanks to a simplified technological process (no junctions), reduced leakage currents and capability to reduce short-channel effects and hot-carrier effects (due to the step in the potential profile induced by the dual-material gate). In this work, we investigate the bipolar amplification and charge collection in JL-DMDG submitted to heavy-ion irradiation. The impact on single-event transients of several parameters such as the length of the high-workfunction gate-material region and of the workfunction of the low-workfunction gate-material region is also particularly addressed. We show that JL-DMDG is more sensitive to radiation than more conventional devices with single-material-gate or operating in inversion-mode.

Bit swapping linear feedback shift register for low power application using 130nm complementary metal oxide semiconductor technology

Bit swapping linear feedback shift register (BS-LFSR) is employed in a conventional linear feedback shirt register (LFSR) to reduce its power dissipation and enhance its performance. In this paper, an enhanced BS-LFSR for low power application is proposed. To achieve low power dissipation, the proposed BS-LFSR introduced the stacking technique to reduce leakage current. In addition, three different architectures to enhance the feedback element used in BS-LFSR was explored. The pass transistor merged with transistor stack method yielded a better reduction in power dissipation compared to pass transistor design and NAND gate design. The BS-LFSR was designed in Mentor Graphic – TSMC Design Kit Environment using 130nm complementary metal oxide semiconductor (CMOS) technology. The proposed 4-bit BS-LFSR achieved an active area of 1241.1588um2 and consumed only 53.8844nW with total power savings of 19.43%. The proposed design showed superiority when compared with the conventional LFSR and related work in reducing power dissipation and area.

Effect of various Fe-doped AlGaN buffer layer of AlGaN/GaN HEMTs on Si substrate

AlGaN/GaN high-electron mobility transistors (HEMTs) with different Fe-doped Al0.25Ga0.75N buffer layers were fabricated on silicon (Si) substrate to improve breakdown voltage and reduce leakage current. Fe doping concentrations for the AlGaN buffer layers were designed as 5 × 1017, 6 × 1017, 7 × 1017, and 8 × 1017 cm−3. The fabricated HEMT with the Fe-doped concentration of 8 × 1017 cm−3 achieved a lower gate leakage current of 8.22 × 10−6 mA/mm, higher breakdown voltage (VBR) of −193 V, and higher buffer breakdown voltage (VBR_buffer) of −1324 V than did other devices with different doping concentrations. In addition, a slight decline in drain current dispersion in pulsed measurements and a slight increase in noise were obtained for HEMTs with a more Fe-doped buffer layer, because the increased Fe-doped concentration resulted in the formation of more buffer traps. However, these results suggest that the HEMT with a highly resistant AlGaN buffer layer of doped Fe has great potential for high-power integrated circuit applications.

Polyethylenimine Insulativity-Dominant Charge-Injection Balance for Highly Efficient Inverted Quantum Dot Light-Emitting Diodes.

Quantum dot (QD) light-emitting diodes (QLEDs) with an inverted architecture suffer from charge-injection imbalance and severe QD charging, which degrade device performance. Blocking excess electron injection into QDs is crucial for efficient inverted QLEDs. It is observed that polyethylenimine (PEI) has two opposite effects on electron injection: one is blocking electron injection by its intrinsic insulativity and the other one is promoting electron injection by reducing the work function of ZnO/PEI. In this work, the insulating nature of PEI has been dominantly utilized to reduce electron injection and the charge-injection balance is realized when PEI becomes thicker and blocks more excess electrons. Furthermore, PEI contributes to QD charging suppression and results in a smoother surface morphology than that of ZnO nanoparticles, which is beneficial for leakage current reduction and QD deposition. As a result, the optimized QLED with 15 nm PEI shows a 2.5 times improved efficiency compared to that of the QLED without PEI. Also, the QLED possesses the maximum external quantum efficiency and current efficiency of 16.5% and 18.8 cd/A, respectively, accompanied with a low efficiency roll-off of 15% at 1000 cd/m2, which is comparable to that of the reported inverted red QLED with the highest efficiency.

Three-Phase CH7 Inverter With a New Space Vector Modulation to Reduce Leakage Current for Transformerless Photovoltaic Systems

Leakage current reduction is crucial for the transformerless photovoltaic inverters. The conventional three-phase current source H6 inverter suffers from the large leakage current, which restricts its application to transformerless PV systems. In order to overcome the limitations, a new three-phase current source H7 (CH7) inverter is proposed in this paper. Only one additional Insulated Gate Bipolar Transistor is needed, but the leakage current can be effectively suppressed with a new space vector modulation (SVM). Finally, the experimental tests are carried out on the proposed CH7 inverter, and the experimental results verify the effectiveness of the proposed topology and SVM method.

EMI and ground leakage current reduction in single‐phase grid‐connected power converter

Ground leakage current in a power converter is a major concern, which has stringent limitations due to safety concerns. Presence of high-frequency pulses, with high d v /d t due to switching actions in common-mode (CM) voltage, result in injection of current waveforms with large d i /d t spikes into the ground and causes high electromagnetic interference (EMI) noise level. In this study, a new method is proposed to make the CM voltage, of a single-phase grid-connected inverter, sinusoidal and free of high-frequency pulses. The proposed method consists of two parallel connected H-bridge power converters, which uses unipolar pulse width modulation (PWM) with carrier interleaving angle of 180°. The proposed method reduces the ground leakage current by more than an order of magnitude. A novel modification to the LCL filter is proposed which further reduces the leakage current by 48%. It is shown that these modifications make the overall system insensitive to circuit non-idealities. Experimental results based on ground leakage current measurements on a 7.5 kW parallel single-phase PWM rectifier are presented. These results validate the effectiveness of the proposed method.

Enhanced magnetization and reduced leakage current by Zr substitution in multiferroic ScMnO3

Despite numerous attempts of electron doping in different manganites (RMnO3, R=rare earth), successful reports are scarce in the literature till date. In this paper, we have synthesized a series of phase-pure electron doped multiferroic compound Sc1−xZrxMnO3 (x=0, 0.05, 0.1, and 0.2) and evaluated the effect of doping on structural properties, oxidation states of cations, DC magnetization, heat capacity, resistivity, dielectric behaviour and ferroelectricity in the material. The presence of Zr4+ and mixed valence state of Mn comprising of Mn2+ and Mn3+ ions are confirmed using X-ray photoelectron spectroscopy. All these samples exhibit antiferromagnetic ordering; as Zr4+ content increases, antiferromagnetic ordering gradually diminishes while shifting to low temperatures. Additionally, ferromagnetic-like interaction develops in doped systems which gives rise to hysteresis in isothermal magnetization loops with greatly enhanced magnetization in comparison to pure antiferromagnetic nature of x=0 i.e. ScMnO3. Interestingly, even with zero magnetic moment of Sc3+, Schottky-like anomaly is observed at 5K in heat capacity data of samples with x=0.1 and 0.2, a result that we attribute to the highly resistive nature of doped samples. Moreover, while measuring ferroelectric hysteresis loops, we observe a significant reduction of leakage current in doped sample (x=0.2) compared to pure ScMnO3. Additionally, the compound x=0.2 shows improved dielectric and ferroelectric behaviour. It is proposed that doping of Zr4+ compensates for the cation deficiency and consequently eliminates the inherent oxygen vacancies by charge compensation.

Improving the electrical and hysteresis performance of amorphous igzo thin-film transistors using co-sputtered zirconium silicon oxide gate dielectrics

The use of co-sputtered Zirconium Silicon Oxide (ZrxSi1−xO2) gate dielectrics to improve the performance of α-IGZO TFT is demonstrated. Through modulating the sputtering power of the SiO2 and ZrO2 targets, the control of dielectric constant in a range of 6.9–31.6 is shown. Prevention of polycrystalline formation of the ZrxSi1−xO2 film up to 600°C annealing and its effectiveness in reducing leakage currents and interface trap density are presented. Moreover, it is revealed that the Zr0.85Si0.15O2 dielectric could lead to significantly improved TFT performance in terms of subthreshold swing (SS=81mV/dec), field-effect mobility (μFE=51.7cm2/Vs), and threshold voltage shift (ΔVTH=0.03V).

Salicide-Like Process for the Formation of Gate and Source Contacts in 4H-SiC TSI-VJFETs

The self-aligned approach allowed to fabricate 4H-SiC VJFETs with conventional contact lithography with only 4 lithography steps. The main problem of this approach was the gate-source leakage current. In order to address this issue, a salicide process has been adopted resulting in a substantial reduction of the gate-source leakage current. The success of this approach paved the way for fabricating high power 4H-SiC devices with extremely low fabrication cost.

Improved leakage current and device uniformity for sub-20 nm N-FinFETs by cryogenic Ge pre-amorphization implant in contact

Prior to contact silicide formation, cryogenic Ge pre-amorphization implantation (PAI) was adopted in sub-20nm FinFETs to investigate how device characteristics can be affected. As compared to room-temperature PAI, cryogenic PAI does not enhance drive current from the viewpoint of mean value, however, it significantly improves variation in device parameters such as sub-Vt swing (SS), drain induced barrier lowering (DIBL) and total series resistance (RTotal) for N-FinFETs by 22%–34% which is due to a reduced number of end of range (EOR) defects caused by Ge PAI. However, the benefit is not observed for P-FinFETs since its source/drain is composed of SiGe which is intrinsically less prone to form EOR defects. In addition, cryogenic PAI also contributes to leakage current reduction for N-FinFETs including gate induced drain leakage (GIDL) by 67%, sub-Vt leakage by 50% and junction leakage by 67% which is primarily due to a lower number of EOR defects that make fewer native point defects. The mechanism for pronounced GIDL reduction for I/O devices than core devices is also proposed. Besides the improved device uniformity as well as leakage current, the process can be fully integrated into incumbent VLSI technology and holds great potential for sub-10nm node.

Effect of Y and Mn doping into rutile type TiO2/Ge stack structure by combinatorial synthesis

The effects of Y and Mn doping into the rutile TiO2 films on a (100) Ge substrate stack structure were investigated by combinatorial synthesis. Composition spread films were fabricated by combinatorial pulsed laser deposition. Regardless of the dopant concentration, the Mn-doped TiO2 film indicated an amorphous structure. In contrast, the Y-doped TiO2 film had a rutile-type crystal structure below an Y concentration of 11.0 at. %. The high Y concentration enhanced the amorphous structure and Ge diffusion into the TiO2 layer. Although both dopants reduced leakage currents, the effect of Y was greater than that of Mn. The post-deposition annealed Y-doped TiO2 indicated an improvement in the leakage current by three orders of magnitude and electron accumulation at a capacitor structure. The Y doping into TiO2 may provide beneficial effects of good interface control and effective dielectric material for Ge-based capacitors.

Comparative analysis of single phase transformerless inverter topologies for grid connected PV system

Many single phase transformerless inverter topologies with reduced leakage current have been introduced for grid tied photovoltaic (PV) applications in the past few years. These topologies are mainly classified on the basis of leakage current reduction methods: galvanic isolation with common mode voltage (CMV) clamping and without CMV clamping. The galvanic isolation can be achieved by incorporation of extra switches either on ac side or dc side of full bridge (H4) inverter topology for ac or dc decoupling respectively. Ac side decoupling offers high efficiency due to lower number of switches in conduction path. However, it has been shown that merely by galvanic isolation, leakage current cannot be reduced to zero, because of stray junction capacitances and resonant circuit effects. Some topologies utilize CMV clamping methods to fix the CMV to half of the dc bus voltage to completely eliminate the leakage current. In this paper, several recently published topologies are reviewed, analyzed and compared. The operation principles of the topologies are discussed with their switching waveforms. The performances of the topologies are compared on the basis of CMV, leakage current, semiconductor device losses, efficiency and total harmonic distortion (THD). A modified CMV clamped H6-IV topology is also proposed to improve common mode characteristics. The analyses are carried out using Matlab/Simulink simulation, and results are verified experimentally.

Analysis and control of improved power quality single‐phase split voltage cascaded converter feeding three‐phase OEIM drive

The use of single phase induction motor (IM) in fuel dispensing units despite its poor efficiency and torque oscillations causing erroneous dispensing etc. is overdue for replacement with 3 phase IM, drives based on single phase AC-DC-AC conversion. But conventional 3 phase IM drive requires high Voltage DC tank capacitor requiring regular replacement due to short life cycle and failure on account of high induced voltage during sudden supply or loads disconnection. This paper presents a new cascaded converter active rectifier (CCAR) unit for splitting single phase to 3 phase to cater variable speed constant v/f controlled open end winding induction motor (OEIM) fuel pump drive. The proposed configuration has an advantage in terms of reduced voltage stress across each split capacitor, reduced leakage current, and distributed voltage stress during sudden supply or load disconnection. A detailed stability analysis is presented in the d - q frame for the control design to access the feasibility of drive operation. The embedded control forces balanced drive operation amidst uneven losses across the H-bridges and /or unbalanced motor loading effect during transients or intermittent operation. The effectiveness of proposed control algorithm is validated both by simulation and experimentation on the developed same scale hardware prototype.

Al2O3/AlGaN Channel Normally-Off MOSFET on Silicon With High Breakdown Voltage

A normally-Off metal-oxide-semiconductor field-effect transistor (MOS-FET) is proposed by using AlInN/AlGaN heterostructure grown on silicon. The AlGaN channel MOSFET with Al2O3 layer as gate insulator exhibits a drain current of 90 mA/mm at the gate bias of +8 V, an ON/OFF drain-current ratio of ${1.4} \times {10}^{8}$ , a peak field-effect mobility of 97 cm2/ $\text {V} \cdot \text {s}$ , and threshold voltage of +2.4 V, respectively. With significant reduction in leakage currents, the MOS-FET with a gate-to-drain spacing of 20 $\mu \text{m}$ delivers a high breakdown of 993 V. The present results of Al2O3/AlGaN normally-Off MOSFET signifies promising prospects for future high power and high voltage applications.