Reduction Of Charge Trapping Research Articles

Influence of air atmosphere on electrical characteristics of p-type MoTe2 FETs under DC and pulsed mode operation

Herein, ambient effects on electrical characteristics of p-type MoTe2 FETs under DC and pulse mode measurements were systematically investigated. As a result of reduced hole concentration in a high vacuum condition, threshold voltage increased as compared to air condition. Moreover, reduction of charge trapping and scattering in vacuum condition leads to electrical performance improvement such as contact resistance, mobility, and interface trap density. Pulsed I-V measurement and CYTOP passivation was additionally introduced to investigate into intrinsic ambient effects by excluding external issues near interface and top channel region. Lastly, temperature dependent mobility variation was examined to validate scattering mechanism in the channel of MoTe2 FETs.

Improving Interface Characteristics of Al2O3-Based Metal-Insulator-Semiconductor(MIS) Diodes Using H2O Prepulse Treatment by Atomic Layer Deposition

We performed temperature dependent current-voltage (I-V) measurements to characterize the electrical properties of Au/Al2O3/n-Ge metal-insulator-semiconductor (MIS) diodes prepared with and without H2O prepulse treatment by atomic layer deposition (ALD). By considering the thickness of the Al2O3 interlayer, the barrier height for the treated sample was found to be 0.61 eV, similar to those of Au/n-Ge Schottky diodes. The thermionic emission (TE) model with barrier inhomogeneity explained the final state of the treated sample well. Compared to the untreated sample, the treated sample was found to have improved diode characteristics for both forward and reverse bias conditions. These results were associated with the reduction of charge trapping and interface states near the Ge/Al2O3 interface.

Bias Temperature Instability (BTI) in high-mobility channel devices with high-k dielectric stacks: SiGe, Ge, and InGaAs

ABSTRACTWe present a review of our recent studies of Bias Temperature Instability (BTI) in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) fabricated with different material systems, highlighting the reliability opportunities and challenges of each novel device family. We discuss first the intrinsic reliability improvement offered by SiGe and Gep-channel technologies, if a Si cap is used to passivate the channel, in order to fabricate a standard SiO2/HfO2gate stack. We focus on SiGe gate stack optimizations for maximum BTI reliability, and on a simple physics-based model able to reproduce the experimental trends. This model framework is then used to understand the suboptimal BTI reliability and excessive time-dependent variability induced by oxide defect charging in different high-mobility channel gate stacks, such as Ge/GeOx/high-k and InGaAs/high-k. Finally we discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability and minimize time-dependent variability.

The Effect of B$^{3+}$ and Ca$^{2+}$Co-Doping on Factors Which Affect the Energy Resolution of Gd$_{{3}}$Ga$_{{3}}$Al$_{{2}}$O$_{{12}}$: Ce

This paper investigates the effects of boron and calcium co-doping on the measured energy resolution of Gd3Ga3Al2O12:Ce (GGAG: Ce). For this study, three samples of GAGG were grown using the Czochralski method. The first sample was doped with Ce3+ and was used as a reference for comparison. The next two samples were additionally doped with either B3+ or Ca2+. The boron co-doped sample was found to have an overall improved performance when compared to the reference sample. The light output of the GGAG:Ce,B was measured to be 10% greater than the reference sample. In addition, the sample was found to have less charge trapping and a more linear relative light yield response. These factors led to an observed improvement in energy resolution from 9% in the reference sample to 7.8% in the B 3+ co-doped sample. Co-doping with Ca2+ led to an overall reduction in charge trapping; however, the sample suffered a 30% reduction in light output, and it was found to have a less linear relative light yield than the reference sample. Its energy resolution was measured to be 10.1%. The relationship between the measured energy resolution and the other measured properties in these samples is discussed.

Reduction of charge trapping in HfO2 film on a Ge substrate by trimethylaluminum pretreatment

AbstractTrimethylaluminum pretreatment prior to HfO2 deposition is introduced for native oxide reduction. It is identified that the trimethylaluminum pretreatment could effectively reduce native oxide, which is transformed to an aluminum oxide interfacial layer. Formation of the thin aluminum oxide layer suppresses Ge diffusion into HfO2, reducing hysteresis in the ca‐ pacitance–voltage curve. Moreover, the device reliability of the trimethylaluminum pretreated sample is improved in a constant current stress test. This work indicates that trimethylaluminum pretreatment is an effective in‐situ method for the gate dielectric stack formation to reduce charge trapping in the HfO2 film on a Ge substrate. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Reduction of Charge Trapping in $\hbox{HfO}_{2}$ Film on Ge Substrates by Atomic Layer Deposition of Various Passivating Interfacial Layers

The dielectric performance and charge trapping properties of $ \hbox{HfO}_{2}$ on a Ge substrate with various passivating interfacial layers (PILs), such as $\hbox{SiO}_{x}\hbox{N}_{y}$ , $\hbox{AlO}_{x}\hbox{N}_{y}$ , $\hbox{HfO}_{x}\hbox{N}_{y}$ , and $\hbox{LaO}_{x}\hbox{N}_{y}$ , are investigated. The large capacitance–voltage ( $C$ – $V$ ) hysteresis of $ \hbox{HfO}_{2}$ on a Ge substrate ( $\sim$ 1500 mV) was not improved by inserting either $\hbox{HfO}_{x}\hbox{N}_{y}$ or $\hbox{LaO}_{x}\hbox{N}_{y}$ PIL between the $\hbox{HfO}_{2}$ and Ge substrates, while both $\hbox{SiO}_{x}\hbox{N}_{y}$ and $\hbox{AlO}_{x}\hbox{N}_{y}$ PILs induced a noticeable reduction of $C$ – $V$ hysteresis. As the PILs' thicknesses increased, the $C$ – $V$ hysteresis of $ \hbox{HfO}_{2}$ with $\hbox{SiO}_{x}\hbox{N}_{y}$ PIL decreased to almost zero, while that of $\hbox{HfO}_{2}$ with $\hbox{AlO}_{x}\hbox{N}_{y}$ PIL decreased but was saturated at approximately 400 mV. Furthermore, the charge trapping property of $ \hbox{HfO}_{2}$ with $\hbox{SiO}_{x}\hbox{N}_{y}$ PIL on a Ge substrate is comparable to that of $\hbox{HfO}_{2}$ grown on a Si substrate. Negligible $C$ – $V$ hysteresis and negligible charge trapping of $\hbox{HfO}_{2}$ with $ \hbox{SiO}_{x}\hbox{N}_{y}$ PIL were understood from the fact that $\hbox{SiO}_{x}\hbox{N}_{y}$ is more resistant to react with a Ge substrate and defective Ge suboxides are efficiently suppressed during the formation of $\hbox{SiO}_{x} \hbox{N}_{y}$ PIL and $\hbox{HfO}_{2}$ layers.

Electrical characteristics of ultrathin gate oxide prepared by postoxidation annealing in ND3

The electrical and reliability characteristics of ultrathin gate oxide, annealed in ND3 gas, have been investigated. Compared with a control oxide, which had been annealed in NH3, the ND3-nitrided oxide exhibits a significant reduction in charge trapping and interface-state generation. The improvement of electrical and reliability characteristics can be explained by the strong Si–D bond at the Si/SiO2 interface. This nitridation process of a gate dielectric using ND3 has considerable potential for future ultra-large-scale integration device applications.

Ultra-thin Gate Oxide Prepared by Nitridation in ND3 for MOS Device Applications

ABSTRACTThe electrical and reliability characteristics of ultra-thin gate oxide, annealed in ND3 gas, have been investigated. Compared with a control oxide, which had been annealed in NH3, the ND3-nitrided oxide exhibits a significant reduction in charge trapping and interface state generation. The improvement of electrical and reliability characteristics can be explained by the strong Si-D bond at the Si/SiO2 interface. This nitridation process of gate dielectric using ND3 has considerable potential for future ultra large scaled integration (ULSI) device applications.

High-quality ultrathin gate oxide prepared by oxidation in D2O

In this letter, we present a process to incorporate deuterium at the Si/SiO2 interface using deuterium oxide (D2O) as an oxidizing gas. We have investigated the electrical and reliability characteristics of ultrathin gate oxide grown in D2O ambient. Compared with a control oxide grown in H2O, an oxide grown in D2O exhibits a significant reduction of charge trapping and interface state generation. Based on secondary ion mass spectroscopy analysis, we found a deuterium-rich layer at the Si/SiO2 interface. The improvement of electrical and reliability characteristics can be explained by the deuterium incorporation at the Si/SiO2 interface.

Ultrathin Gate Oxide Prepared by Oxidation in D2O for Mos Device Applications

ABSTRACTWe present a novel gate oxidation process using D2O (deuterium oxide) as an oxidizing gas. The electrical and reliability characteristics of ultrathin gate oxide grown in D2O ambient have been investigated. Compared with a control oxide grown in H2O, a oxide grown in D2O exhibits a significant reduction of charge trapping and interface state generation. Based on a secondary ion mass spectroscopy (SIMS) analysis; we found a deuterium rich-layer at the Si/SiO2 interface. The improvement of electrical and reliability characteristics can be explained by the deuterium incorporation at the Si/SiO2 interface.

Novel interface nitridation process for thin gate oxides

A thin (100-200-AA) gate dielectric film which exhibits improved properties as compared to control pure thermal oxides is discussed. The film is obtained by thermal nitridation of the silicon wafers in pure ammonia, followed by high temperature oxide (HTO) deposition, and an anneal in oxygen ambient (reoxidation). It was found that these dielectrics exhibit excellent electrical characteristics under Fowler-Nordheim tunneling stress, such as a relatively large charge-to-breakdown considerable reduction in charge trapping, reduction of interface state generation, and a significantly improved resistance to transconductance degradation. The dielectric layer is of potential use for the fabrication of reliable ultrathin gate oxide films for standard CMOS technology and particularly for nonvolatile programmable memories. >

Gate bias polarity dependence of charge trapping and time-dependent dielectric breakdown in nitrided and reoxidized nitrided oxides

The gate bias polarity dependence of charge trapping and time-dependent dielectric breakdown (TDDB) in nitrided and reoxidized nitrided silicon dioxides prepared by rapid thermal processing (RTP) is reported. Charge trapping during high-field injection can be reduced by rapid thermal nitridation for both substrate and gate injection. While reoxidation of nitrided oxides shows further reduction in charge trapping for substrate injection, degradation is observed for gate injection. Similar effects are observed for TDDB: reoxidized nitrided oxides show charge-to-breakdown in excess of 300 C/cm/sup 2/ for substrate injection, but less than 30 C/cm/sup 2/ for gate injection. These effects are related to the nitrogen and hydrogen profiles in the oxides. By tailoring the process conditions, a symmetric behavior of NO and RONO films with low charge trappings and Q/sub BD/ in excess of 50 C/cm/sup 2/ is possible, making them attractive as long-lifetime dielectrics from EEPROM (electrically erasable programmable ROM) and flash EEPROM technologies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>