Reduction In Total Power Dissipation Research Articles

Thermally Aware LVCMOS based Low Power Universal Asynchronous Receiver Transmitter Design on FPGA

Green communication is the latest research trend practiced by researcher in green computing and network communication. There is no extensive work in green UART design. In order to fill this research gap, we are going to design LVCMOS based energy efficient Universal Asynchronous Receiver Transmitter (UART) that will create an avenue for IO standards based green communication. UART (Universal Asynchronous Receiver Transmitter) is a kind of serial communication protocol; mostly used for short-distance low speed, low-cost data exchange between computer and peripherals. Various energy efficient techniques have been applied to the design along with the change in IO standards. It has been concluded that there occurs 97.65% reduction in clock power, 75.14% reduction in I/O power, 7.19% reduction in leakage power, 17.37% reduction in junction temperature, and 71.12% reduction in total power dissipation in case SSTL2_II IO/standard, thus it is considered to be most energy and power efficient IO standard to be used in the future.

LVCMOS and BLVDS Based Energy Efficient Counter Design on 28nm FPGA

Counter play an important role in design of stopwatch, countdown of space craft, rocket, launcher and so on. In this work, we are going to design energy efficient counter. For that we are exploring 10 different configuration of counter and find the most energy efficient counter among them. For further reduction of power dissipation of the most efficient counter, we are using different Input/Output standards and select the most energy efficient IO standards for counter. 8 bit Up counter with Load has maximum reduction in total power among 10 different counters. When we use LVCMOS15, LVCMOS18, LVCMOS25, and LVCMOS33 in place of BLVDS_25 then there is 65-81% reduction in total power dissipation in 8 bit Up counter with Load. As we move down the column from LVCMOS15 to LVCMOS33 there is 94-77% reduction in IO power Dissipation and leakage power variation is very less. Keywords—Counter, LVCMOS, BLVDS, FPGA, Energy Efficient, clock, enable, up down counter, one hot counter, random LFSR counter, divide by 3 counter.

Data Encoding Schemes in Networks on Chip

An ever more significant fraction of the overall power dissipation of a network-on-chip (NoC) based system-on-chip (SoC) is due to the interconnection system. In fact, as technology shrinks, the power contribute of NoC links starts to compete with that of NoC routers. In this paper, we propose the use of data encoding techniques as a viable way to reduce both power dissipation and energy consumption of NoC links. The proposed encoding scheme exploits the wormhole switching techniques and works on an end-to-end basis. That is, flits are encoded by the network interface (NI) before they are injected in the network and are decoded by the destination NI. This makes the scheme transparent to the underlying network since the encoder and decoder logic is integrated in the NI and no modification of the routers architecture is required. We assess the proposed encoding scheme on a set of representative data streams (both synthetic and extracted from real applications) showing that it is possible to reduce the power contribution of both the self-switching activity and the coupling switching activity in inter-routers links. As results, we obtain a reduction in total power dissipation and energy consumption up to 37% and 18%, respectively, without any significant degradation in terms of both performance and silicon area.

Supply and power optimization in leakage-dominant technologies

In this paper, we present a methodology for systematically optimizing the power-supply voltage for either maximizing the performance of very large scale integration (VLSI) circuits or minimizing the power dissipation in technologies where leakage power is not an insignificant fraction of the total power dissipation. For this purpose, we develop simplified empirical equations that describe the transistor behavior as a function of power supply and temperature. We use these models to calculate the full-chip power dissipation as a function of power supply and temperature. We then solve the power and chip thermal equations simultaneously to calculate the chip temperature and power dissipation at a given power supply. By varying the power-supply voltage, we determine the optimum V/sub DD/ value that minimized delay per unit length in global interconnects and therefore maximizes performance. Using the same framework, by again varying the supply we find the optimum V/sub DD/ that minimized the total power dissipation while maintaining a given delay per unit length. We show that for 90- and 65-nm technologies, where leakage power represents a significant fraction of the total power dissipation, optimum V/sub DD/ for maximum performance is lower than the International Technology Roadmap for Semiconductors (ITRS) specified supply voltage. This is due to the fact that reducing V/sub DD/ results in a large reduction in total power dissipation, and therefore the chip temperature, which improves performance. This improvement in performance is greater than the performance penalty incurred due to reduction in V/sub DD/. We also show that as the required delay per unit length is increased, total chip power consumption is reduced significantly if the power supply is also reduced as compared to the case when power supply is fixed at the nominal value. This change becomes larger with technology scaling due to the fact that leakage power, which is a very strong function of chip temperature, becomes a larger fraction of the full-chip power dissipation.

A coding framework for low-power address and data busses

This paper presents a source-coding framework for the design of coding schemes to reduce transition activity. These schemes are suited for high-capacitance buses where the extra power dissipation due to the encoder and decoder circuitry is offset by the power savings at the bus. In this framework, a data source (characterized in a probabilistic manner) is first passed through a decorrelating function f/sub 1/. Next, a variant of entropy coding function f/sub 2/ is employed, which reduces the transition activity. The framework is then employed to derive novel encoding schemes whereby practical forms for f/sub 1/ and f/sub 2/ are proposed. Simulation results with an encoding scheme for data buses indicate an average reduction in transition activity of 36%. This translates into a reduction in total power dissipation for bus capacitances greater than 14 pF/b in 1.2 /spl mu/m CMOS technology. For a typical value for bus capacitance of 50 pF/b, there is a 36% reduction in power dissipation and eight times more power savings compared to existing schemes. Simulation results with an encoding scheme for instruction address buses indicate an average reduction in transition activity by a factor of 1.5 times over known coding schemes.