Reduction In On-state Resistance Research Articles

Effects of high in-situ source/drain boron doping in p-FinFETs on physical and device performance characteristics

In this study, the effects of high in-situ boron (B) doping in embedded source/drain (S/D) silicon germanium (SiGe) stressor of p-channel Fin Field Effect Transistors (FinFETs) in a 14 nm technology node were investigated. The device results were correlated to physical characteristics of B doped S/D regions which were probed using Transmission Electron Microscopy (TEM), Electron Energy Loss Spectroscopy (EELS) and Low Energy Electron Induced X-ray Emission Spectroscopy (LEXES) on representative device structures. B doping was established to be around low-E20 atoms/cm3 range as measured by LEXES. Reduction in on-state resistance (RON) and an increase in drive current (ION) was observed with higher B doping in SiGe but physical constraints, especially B segregation offered manufacturable challenges. These observed results are expected to critically help in SiGe stressor based S/D junction optimization of advanced FinFET Complementary Metal-Oxide-Semiconductor (CMOS) devices.

In0.53Ga0.47As/InP Trench-Gate Power MOSFET Based on Impact Ionization for Improved Performance: Design and Analysis

A novel In0.53Ga0.47As/InP heterostructure trench-gate power MOSFET employing impact ionization at the hetero junction of n− In0.53Ga0.47As drift region and n+InP drain region has been proposed. The impact ionization supports the band-to-band tunneling at heterojunction, which further increases the drain current. It results in reduced ON-state resistance and improved transconductance without compromising with the breakdown voltage as compared with the conventional silicon trench-gate MOSFET (CTGMOS). Using 2-D numerical simulations, we demonstrate that the proposed device exhibits ~440% improvement in peak transconductance, ~92% reduction in on-state resistance, ~ 10% increase in breakdown voltage, ~16% increase in switching speed, and ~93% improvement in figure of Merit ( ${\text {R}}_{\textsf {ON}}$ . ${\text{Q}}_{\textsf {GD}})$ as compared with CTGMOS.

Coolmos Technology – Outstanding Prospects towards Idealized Power Semiconductor Switch

CoolMOS technology – developed for the production of charge-compensated devices – is presented. Due to its novel internal structure, the derice offers a dramatic reduction in on-state resistance with a completely altered voltage dependence of the device capacitances. Ruggedness aspects such as avalanche and short-circuit behavior are excellent and reach the limits of active zener-clamped devices. The above-mentioned electrical characteristics make the device suitable for a broad range of applications. The paper also discusses device physics-based selection criteria for fast IGBTs and CoolMOS.The paper describes innovative SPICE and SABER simulation models incorporating a dynamic connection between electrical and thermal component description. On the one hand this enables the realistic simulation of operating states in which a relevant self-heating effect occurs. On the other, the models provide defined thermal nodes which create a connection to the thermal environment of the component and thus, for example, facilitate the investigation and optimization of hearsink options.

Characteristics of p-channel polysilicon conductivity modulated thin-film transistors

A p-channel polysilicon conductivity modulated thin-film transistor (CMTFT) is demonstrated and experimentally characterized. The transistor uses the concept of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. The conductivity modulation is achieved by injecting minority carriers (electrons) into the offset region through a diode added to the drain. Experimental results show that the conductivity modulation in the p-channel device is as effective as that in the n-channel device. This structure can provide 1.5 to 2 orders of magnitude higher on-state current than that of the conventional offset drain thin-film transistor (TFT) at drain voltage ranging from -15 V to -5 V while still maintaining low leakage current and simplicity in device operation. The p-channel CMTFT can be combined with the n-channel CMTFT to form CMOS high-voltage drivers, which is very suitable for use in fully integrated large-area electronic applications.

A Conductivity Modulated Polysilicon Thin-Film Transistor

This paper reports a novel high voltage Conductivity Modulated Thin-Film Transistor (CMTFT) fabricated using polycrystalline silicon. The transistor uses the idea of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. Experimental on-state and off-state current-voltage characteristics of the CMTFT have been compared with those of the conventional offset drain device. Results show that the CMTFT has six times to more than three orders of magnitude higher on-state current handling capability for operating at drain voltages ranging from 15 V to 5 V while still maintaining low leakage current and providing even faster switching speed. The CMTFT devices can be fabricated using a low temperature process (620/spl deg/C) which is highly desirable for large area electronic applications. >