Noise Figure Reduction Research Articles

Design of Low Noise Amplifier for IEEE Standard 802.11b Using Cascode and Modified Cascode Techniques

This paper presents the performance comparison of two Low Noise Amplifiers (LNA), a basic Cascode and a modified cascode LNA for IEEE 802.11b protocol, WLAN. A modified cascode LNA with dual Common source transistors is designed and the performance parameters are compared with a designed basic cascode stage. The modified cascode stage has a high gain of 19.2dB and an optimized noise figure of 0.416dB at 2.4 GHz and at a supply voltage of 1.8V. The S11 is -13.74dB, S22 is -0.87dB and S12 is -43.63dB. The P1dB is -18.35dBm and the IIP3 is -8.42dBm. The LNA is designed to be stable over 2-3 GHz range. The power consumption of the circuit is 8.1mW. The modified cascode LNA is having around 10% improvement in gain and a 40% reduction in noise figure compared to the basic Cascode LNA. The simulations are done in cadence virtuoso Spectre RF using 180 nm technology.

Influence of ASE Noise on the Performance of DWDM Networks Using Low-Power Pumped Raman Amplifiers

ABSTRACTWe present the results of investigation of influence of amplified spontaneous emission (ASE) noise, noise figure (NF) and dispersion chromatic on the performance of middle-distance dense-wavelength-division-multiplexing (DWDM) networks using low-power pumped distributed Raman amplifiers (DRAs) in two different pump configurations, i.e., forward and backward pumping. We found that the pumping configurations, ASE noise, and dispersion play an important role for improving the network performance by reduction of NF and bit error rate (BER) of the system. Simulation results show that the lowest BER and low NF were obtained, when using the forward pumping configuration. Moreover, we have also compared ASE noise powers of the simulation with this experiment. These results conclude that DRA with low pump power (<1 W) is the promising key technology for short- and/or middle-distance DWDM transmission networks.

Analysis and design of low noise transconductance amplifier for selective receiver front-end

Analysis and design of a low-noise transconductance amplifier (LNTA) aimed at selective current-mode (SAW-less) wideband receiver front-end is presented. The proposed LNTA uses double cross-coupling technique to reduce noise figure (NF), complementary derivative superposition, and resistive feedback to achieve high linearity and enhance input matching. The analysis of both NF and IIP3 using Volterra series is described in detail and verified by SpectreRF® circuit simulation showing NF +17 dBm and blocker P1dB >+5 dBm over frequency range of 0.5---3 GHz.

Co-design Approach for Wide-Band Asymmetric Cross Shaped Slotted Patch Antenna with LNA

The proposed work presents a co-design approach for a new asymmetric rectangular cross shaped slotted patch antenna with low noise amplifier that occupies 17.2---25.8 GHz wide-band for SDR applications. This co-design approach minimizes the chip area and noise and also improves integration system over the bandwidth of 8.6 GHz. Three different architectures have been designed in this work. Firstly, a two stage CMOS CG---CS LNA is designed using a technique of series---parallel resonant network as an input matching network and as inter-stage matching network between CG and CS LNA. In second architecture stage, a rectangular shaped microstrip antenna is designed and a slot of asymmetric cross shape is cut on the patch antenna. In third architecture the slotted antenna is integrated with low noise amplifier in order to form a co-design approach in which series---parallel resonant network is used as a band pass filter between slotted patch antenna and LNA. A two-stage CMOS LNA design is simulated and layout is made using foundry design kit for the TSMC 65 nm CMOS process in ADS.v.12. A simulation result of LNA achieves S11 of ?21.4 dB with gain ranging from 7.4 to 21.3 dB over the wide-band of 19.1---28.8 GHz. The slotted antenna achieves S11 of ?19 dB at 26 GHz and covers frequency range of 20.1---27.8 GHz with good radiation and receiving patterns. This co-design approach is analysed considering the 50 ? impedance matching throughout the design and simulated on the platform of ADS.v.12. The best achievement of proposed co-design approach is reduced noise figure which is most suitable for SDR applications.

A Compact, Supply-Voltage Scalable 45–66 GHz Baseband-Combining CMOS Phased-Array Receiver

This paper presents a four-element phased-array receiver which achieves 38% fractional bandwidth around 55 GHz. Baseband phase-shifting is employed to eliminate wideband phase-shifters, power dividers, and quadrature splitters operating at millimeter-wave frequencies. Antenna weighting and combining are accomplished using a highly digital Cartesian phase-shifter and current summation, respectively. Transformer-coupling techniques are introduced in the LNA to simultaneously achieve wide bandwidth, reduced noise figure, gain boosting and neutralization. Cascode-free and folded topologies are used throughout to enable operation from a scalable supply voltage. To overcome challenges associated with wideband LO distribution, the LO network employs multiconductor transmission lines to distribute four-phase LO signals. The LO distribution network is absorbed into the LO buffers and terminated by distributed LC loads near the I/Q mixers in each phased-array element. The phased-array receiver is fabricated in a 45 nm SOI CMOS process and achieves 26.2 dB (20.2 dB) of element gain over 21 GHz (19 GHz) of 3 dB bandwidth with 5.5 dB/9.8 dB (7.7 dB/12 dB) minimum/maximum NF while dissipating 30 mW/element (14 mW/element) from a 1.1 V (0.6 V) supply voltage. The worst case -1 dB (input) compression is -28 dBm at 1.1 V. A worst case coupling of 26 dB (45 dB) is measured between adjacent (nonadjacent) elements. The IF bandwidth is 1.2 GHz, limited by the wirebond and PCB interface to the chip. The design occupies only 0.225 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per element including LO buffer/distribution.

Noise figure reduction by port decoupling for dual circular polarised microstrip antenna

A planar dual circular polarised (CP) feed is highly desirable for dish-type satellite communication terminals, but isolation between ports is typically poorer for CP microstrip antennas than for linearly polarised elements. Mutual coupling between the output ports of a dual CP planar feed can affect the equivalent noise temperature of the satellite ground terminal receiver. A port decoupling network is designed for a single-layer dual CP microstrip antenna to increase the isolation to >20 dB between the antenna ports while maintaining CP quality. The effect of decoupling for the single-layer dual CP feed on the performance of a high sensitivity dual polarised receiver for satellite communication applications is analysed.

0.7–2.7 GHz wideband CMOS low‐noise amplifier for LTE application

A wideband low-noise amplifier (LNA) for long-term evolution applications is presented. A capacitive cross-coupled common-gate in combination with current-bleeding common-source topologies is adopted for wideband input matching, high gain and low noise figure (NF). Inter-cascade inductors are adopted to cancel the inter-stage parasitics, which extend input matching and operational bandwidth to higher frequency with additional NF reduction. Implemented in a 0.18 µm CMOS technology, the proposed wideband LNA shows a voltage gain of 17 dB, a NF of < 2.5 dB, |S 11| of higher than 10 dB and a maximum IIP3 of + 1.52 dBm over the frequency range of 0.7–2.7 GHz while consuming 7.5 mA from a 1.8 V supply.

Design of a high gain and highly linear common-gate UWB mixer in K-band

In this paper, in order to design a K-band common-gate Gilbert-cell mixer via a 0.18 μm CMOS technology, the ?-Network and post-distortion cancellation (PDC) techniques are implemented simultaneously, resulting in the improvement of gain, bandwidth, noise figure and linearity. Also, a new method for implementing the ?-Network, using the parasitic capacitances between RF and LO stage nodes, is proposed which improves the mixer performance and makes the mixer design possible at high frequencies. It is shown that the ?-Network enhances the gain and bandwidth by generating complex poles in system frequency response without the need for extra power consumption. The suitable location of these poles, which gives rise to high gain and high bandwidth, is discussed and determined by MATLAB simulation. Results of simulation illustrate 3.36 dB improvement in power conversion gain and 2 dB reduction in noise figure at the same power consumption with LO power of ?1 dBm in comparison with the case when PDC technique is used only. Compared to conventional mixer, it improves the IIP3 by 6 dB. Also, the power consumption of the mixer together with the designed bias circuit is 9.68 mW at 1.8 V.

Design of Low Power 2.4GHz CMOS Cascode LNA with Reduced Noise Figure for WSN Applications

In this paper, a narrowband cascode Low Noise Amplifier (LNA) with shunt feedback is proposed. A typical inductively degenerated cascode LNA can be treated as a Common Source-Common Gate (CS-CG) two stage LNA. The series interstage inductance is connected between CS-CG stages to increase the power gain. An additional inductance which is connected at the gate of CG stage is used to cancel out the parasitic capacitance of CG stage therefore reduces the noise figure of CG stage. The shunt feedback is used to improve the stability and input impedance matching. This configuration provides better input matching, lower noise figure, low power consumption and good reverse isolation. The proposed LNA exhibits the gain of 13 dB, input return loss of ?11 dB, noise figure of 2.2 dB and good reverse isolation of ?42.8 dB at a frequency of 2.4GHz using TSMC 0.13 μm CMOS technology. It produces gain and noise figure better than conventional cascode LNA. The proposed LNA is biased in moderate inversion region for achieving sufficient gain with low power consumption of 1.5mW at a supply voltage of 1.5V.

A Low Power Inductorless LNA With Double ${\rm G} _{\rm m}$ Enhancement in 130 nm CMOS

This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CMOS technology for 2.45 GHz ISM band applications. The circuit benefits from several gm-enhancements. These techniques provide a high gain and reduced Noise Figure (NF) in spite of the low intrinsic gm of the MOS transistors. Moreover, the circuit is fully inductorless. Main design points are described and the performance tradeoffs of the circuit are discussed. A prototype has been implemented and it exhibits a 20 dB gain with a 4 dB NF while dissipating 1.32 mW. The IIP3 is -12 dBm for an input compression point of -21 dBm.

On-Chip Inductor Technique for Improving LNA Performance Operating at 15 GHz

This paper presents a technique for low noise figure reduction of low-noise amplifier (LNA). The proposed LNA is designed in a source degeneration technique that offers lower noise figure. The resistance of the on-chip inductor is reduced by using multilayer that significantly reduces the thermal noise due to spiral inductor. Also, using spiral inductor as a gate inductor reduces the effect of the input parasitic capacitance on the noise figure and provides a good matching at the input and output of the LNA. The results of the LNA using multilayer on-chip inductor compared will off-chip inductor have been illustrated. It shows that the proposed technique reduces significantly the noise figure and improves the matching. The proposed LNA is designed in 0.13 μm process with 1.3 V supply voltage and simulated using Advanced Design System (ADS) software. The simulation results show that the LNA is unconditionally stable and provides a forward gain of 11.087 dB at operating frequency of 15 GHz with 1.784 dB noise figure and input and output impedance matching of –17.93 dB, and –10.04 dB.

PENURUNAN NOISE FIGURE PERFORMANCE (FN) PADA HETEROJUNCTION BIPOLAR TRANSISTOR SI/SI 1-X GEX BERDASARKAN PENGATURAN STRIPE EMITTER AREA (AE) DAN FRACTION MOLE (X)

Reduction of Noise Figure (Fn) on Bipolar Heterojunction Si/Si1-x Gex based on Arrangements Stripe Emitter Area (Ae) and Mole Fraction (x). This paper investigates the influence of stripe emitter area (Ae) and fraction mole (x) concerning about noise figure performance (FN) at HBT SiGe. It takes the second generation of HBT SiGe IBM with Ae; 0.18 x 10 μm2 developed as its model. When the alterations of Ae are from 0.18 x 10 μm2, 0.12 x 10 μm2 and 0.09 x 10 μm2, at the same time the fraction mole (x) is raised twice, it makes positive relation to RB and β parameter, but negative relation to RC, fT, and fmax parameter. A model of HBT SiGe with x: 0.1 and Ae: 0.18 x 10 μm2 produces 0.57dB of Fn minimum, the value is less than the other of which has 0.64dB for Ae: 0.12 x 10 μm2 and 0.69 dB for Ae: 0.09 x 10. Then if fraction mole(x) is reduced for 50%, it causes nonlinear Fn raising which are 77%, 79% and 89% from the previous value. Noise figure (Fn) had a negative relationship with emitter stripe area (Ae), whereas the mole fraction (x) has a positive relationship; so the noise figure (Fn) can be made low by minimizing emitter stripe area (Ae) and raise the mole fraction (x).

Hybrid flat gain C-band optical amplifier with Zr-based erbium-doped fiber and semiconductor optical amplifier

An efficient gain-flattened C-band optical amplifier is demonstrated using a hybrid configuration with a Zirconia-based Erbium-doped fibre (Zr-EDF) and a semiconductor optical amplifier (SOA). The amplifier utilizes a two-stage structure with a midway isolator to improve flat gain characteristic and reduce noise figure. At input signal power of −30 dBm, a flat gain of 28 dB is obtained from wavelength region of 1530 to 1560 nm with gain variation of less than 4 dB. The noise figure is maintained below 11 dB at the flat-gain region. This amplifier has the potential to be used in the high channel count dense wavelength division multiplexing system due to its simplicity and compact design.

A Weak-Resonant-Cavity Fabry–Perot Laser Diode With Injection-Locking Mode Number-Dependent Transmission and Noise Performances

Quasi-color-free weak Fabry-Perot cavity laser diode with long cavity length is one alternative solution of the wavelength-division-multiplexed passive optical network (WDM-PON) transmitter with comparable broadband gain spectrum and greatly reduced noise figure as compared to typical reflective semiconductor optical amplifiers. In this paper, the amplified spontaneous emission injection-locked weak-resonant-cavity Fabry-Perot laser diode (WRC-FPLD) with 1% front-facet reflectivity directly modulated at 1.25 Gbit/s with detuning injection-locked mode for quasi-color-free transmission in WDM-PON system with channel spacing of 200 GHz is demonstrated. With bias current changing from 0.9 Ith to 1.4 Ith, the improvement on receiving power sensitivity for the WRC-FPLD-based WDM-PON transmitter is up to 9 dB at bit error rate (BER) of 10-9. Increasing the injection-locked mode number from 2 to 3 within temperature variation of 6°C effectively promotes the BER from 10-8 to 10-10 at receiving power of -27 dBm associated with a decreasing power penalty of -3.2 dB. The WRC-FPLD with more injection-locked modes within one channel exhibits higher extinction ratio at higher operating temperature within one injection-locked-mode-number changing period. This elucidates well the cycling evolution on the BER performance of the WRC-FPLD as a function of operating temperature.

Experimental Investigation of RF Noise Performance Improvement in Graded-Channel MOSFETs

In this paper, measured RF noise performance of graded-channel metal-oxide-semiconductor (MOS) transistors (GCMOS - also named laterally asymmetric channel transistors) shows impressive reduction in minimum noise figure ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NF</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> ) as compared to classical MOSFET transistors (with the same gate length <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Lg</i> = 0.5 mum). The reason is proven to be because of the higher noise correlation coefficient ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> ). GCMOS also shows lower sensitivity to extrinsic thermal noise as compared to classical MOSFET. Moreover, it is demonstrated that the use of 0.5- mum-gate-length GCMOS gives a competitive RF noise performance as compared to 0.25-mum-gate-length classical nMOS transistors.

A Low Voltage Mixer With Improved Noise Figure

A 5.2 GHz low voltage mixer with improved noise figure using TSMC 0.18 mum CMOS technology is presented in this letter. This mixer utilizes current reuse and ac-coupled folded switching to achieve low supply voltage. The noise figure of the mixer is strongly influenced by flicker noise. A resonating inductor is implemented for tuning out the parasitic components, which not only can improve noise figure but also enhance conversion gain. A low voltage mixer without resonating technique has also been fabricated and measured for comparison. Simulated results reveal that flicker corner frequency is lowered. The measured results show 4.5 dB conversion gain enhancement and 4 dB reduction of noise figure. The down-conversion mixer with resonating inductor achieves 5.8 dB conversion gain, -16 dBm P1dB, -6 dBm IIP3 at power consumption of 3.8 mW and 1 V supply voltage.

Sub-0.2 dB Noise Figure Wideband Room-Temperature CMOS LNA With Non-50 $\Omega$ Signal-Source Impedance

This paper presents a wideband low-noise amplifier (LNA) designed to be used as the first stage of the receiver in the Square Kilometer Array radio telescope. The LNA design procedure and its layout features are discussed. The noise figure optimization procedure determines the signal-source resistance that results in reduced noise figure. When used in the radio telescope, the required signal-source resistance will be presented by the telescope custom-made antenna elements. The LNA, designed in 90 nm bulk CMOS, achieves sub-0.2 dB noise figure from 800 MHz to 1400 MHz, return loss of more than 11 dB, gain of more than 17 dB driven into a 50 load, output 1 dB compression point of 2 dBm, output IP3 of 12 dBm, and output IP2 of 22 dBm while consuming 43 mA from a 1 V supply. In the LNA implementation presented in this paper the load choke inductor and the source inductor are integrated whereas the gate-, bias-, and the choke-inductor between two transistors of the cascode are external. The noise figure of the presented LNA is to our knowledge the lowest noise figure achieved by a power matched wideband CMOS LNA at room temperature.

Corrections to "Noise Figure Reduction in Externally Modulated Analog Fiber-Optic Links"

Corrections to "Noise Figure Reduction in Externally Modulated Analog Fiber-Optic Links"

Noise Figure Reduction in Externally Modulated Analog Fiber-Optic Links

An octave-bandwidth microwave photonic link with a third-order limited spurious-free dynamic range of 121 dB in a 1-Hz bandwidth has been demonstrated. The link noise figure of 9 dB at a modulation frequency of 2 GHz was achieved by using a bias-shifted Mach-Zehnder modulator with an optical input power of 500 mW. This level of performance was realized without electronic or optical linearization

Optimizing the incoherent pump spectrum of low-gain-ripple distributed fiber Raman amplifier for a given main pump wavelength

The method for designing the incoherent pump spectrum for the distributed fiber Raman amplifiers (DFRAs) of low gain ripple is studied, in which the wavelength of the maximum power spectral density can be assigned. The assigned wavelength is called the main pump wavelength. Incoherent pump spectrum is described with the power spectral density function (PSDF) that comprises a set of piece-wise continuous functions. PSDF is optimized for the minimum gain ripple with the least-square minimization method. An extremum pump wavelength condition is applied to PSDF. A proper initial trial PSDF is given so that the optimized PSDF converges to the desired result and the power spectral density at the extremum pump wavelength is the maximum. With this design method, we show the optimized PSDFs for the DFRAs using backward pumping and bidirectional pumping. The gain ripples of considered DFRAs are less than 0.1 dB for 20-dB ON-OFF Raman gain over 70-nm bandwidth. The reduction of average effective noise figure with shorter main pump wavelength is shown and investigated.