Feature Size Reduction Research Articles

Advanced metrology needs for nanoelectronics lithography

The semiconductor industry has exploited productivity improvements through aggressive feature size reduction for over four decades. While enormous effort has been expended in developing the optical lithography tools to print ever finer features, significant advances have also been required to measure the printed features. In this article we will discuss the current state of the art in the metrology for measuring critical dimensions of printed features for scanning electron microscopy and atomic force microscopy, and describe work at the National Institute of Standards and Technology advancing these tools as well as exploratory work on two new promising techniques, scatterfield microscopy and small angle X-ray scattering. Line width roughness critical dimension and overlay metrology and control are two of the most significant industry needs mentioned in the International Technology Roadmap for Semiconductors (2005). To cite this article: S. Knight et al., C. R. Physique 7 (2006).

An Oligonucleotide Microarray for High-Throughput Sequencing of the Mitochondrial Genome

Previously we developed an oligonucleotide sequencing microarray (MitoChip) as an array-based sequencing platform for rapid and high-throughput analysis of mitochondrial DNA. The first generation MitoChip, however, was not tiled with probes for the noncoding D-loop region, a site frequently mutated in human cancers. Here we report the development of a second-generation MitoChip (v2.0) with oligonucleotide probes to sequence the entire mitochondrial genome. In addition, the MitoChip v2.0 contains redundant tiling of sequences for 500 of the most common haplotypes including single-nucleotide changes, insertions, and deletions. Sequencing results from 14 primary head and neck tumor tissues demonstrated that the v2.0 MitoChips detected a larger number of variants than the original version. Multiple coding region variants detected only in the second generation MitoChips, but not the earlier chip version, were further confirmed with conventional sequencing. Moreover, 31 variations in noncoding region were identified using MitoChips v2.0. Replicate experiments demonstrated >99.99% reproducibility in the second generation MitoChip. In seven head and neck cancer samples with matched lymphocyte DNA, the MitoChip v2.0 detected at least one cancer-associated mitochondrial mutation in four (57%) samples. These results indicate that the second generation MitoChip is a high-throughput platform for identification of mitochondrial DNA mutations in primary tumors.

Feature-size reduction of photopolymerized structures by femtosecond optical curing of SU-8

The universal scaling of a width of photopolymerized line on the exposure dose was observed in polymerization by direct laser writing using tightly focused femtosecond pulses in SU-8 resist. This scaling can be explained as the photopolymerization by a blackbody-type emission. A spectrally broad thermal emission of electrons heated up to temperatures approximately Te∼103K coincides with an IR-absorption band of SU-8 centered at the 2.9μm and had caused polymerization by a cumulative direct absorption. Three-dimensional photonic crystal templates with approximately twice reduced feature size were fabricated with stop band at the fiber communication wavelength of 1.3μm.

Future of high pressure liquid chromatography: Do we need porosity or do we need pressure?

Making a theoretical study supported by experiments of the kinetic advantages of increased inlet pressures versus increased external porosity using impedance plots of analysis time versus required plate number, it is found that both approaches more or less have the same effect on the kinetic performance. The need to change a given system to one with an increased inlet pressure or with an increased external porosity can best be assessed from the optimal plate number ( N opt) of the system. When the pursued application requires a plate number that is larger than N opt, any increase in inlet pressure and external porosity is beneficial. When the required plate number is smaller than N opt, any increase in inlet pressure and external porosity should preferentially be accompanied by an overall reduction of the feature sizes of the support. The degree to which this feature size reduction can be realized in practice will to a large extent determine which of the two approaches will be the dominant system of the future.

Sub-10-nm high aspect ratio patterning of ZnO in a 500μm main field

We demonstrate the fabrication of sub-10-nm high aspect ratio electron beam patterning of ZnO at the center as well as corners of the 500μm square main deflection field using a negative tone zinc naphthenate resist. After electron beam exposure, the resist was developed in toluene, resulting in high-resolution patterns as small as 7nm with an aspect ratio of ∼10 in the center as well as at the corners of the main field. The line edge roughness (3σ) of these lines shows roughness with fluctuations of about 2.8nm; thus making it the smallest value of the line edge roughness measured so far for any electron beam resist. Heating the structures at 500°C resulted in reduction of feature sizes to ∼5nm and in the formation of crystalline ZnO. Such sub-10-nm high aspect ratio patterning within the main deflection field is an important step to enable full-wafer-level nanofabrication.

Lattice Boltzmann Modeling of Subcontinuum Energy Transport in Crystalline and Amorphous Microelectronic Devices

AbstractNumerical simulations of time-dependent energy transport in semiconductor thin films are performed using the lattice Boltzmann method applied to phonon transport. The discrete lattice Boltzmann method is derived from the continuous Boltzmann transport equation assuming first gray dispersion and then nonlinear, frequency-dependent phonon dispersion for acoustic and optical phonons. Results indicate that a transition from diffusive to ballistic energy transport is found as the characteristic length of the system becomes comparable to the phonon mean free path. The methodology is used in representative microelectronics applications covering both crystalline and amorphous materials including silicon thin films and nanoporous silica dielectrics. Size-dependent thermal conductivity values are also computed based on steady-state temperature distributions obtained from the numerical models. For each case, reducing feature size into the subcontinuum regime decreases the thermal conductivity when compared to bulk values. Overall, simulations that consider phonon dispersion yield results more consistent with experimental correlations.

Electric Field Guided Self-Assembly of Molecules

ABSTRACTAdsorbate molecules usually carry electric dipole moments, and the magnitude can be engineered by adding polar groups. This paper investigates the dynamic domain pattern formation of multilayer dipolar molecules on a substrate under the guidance of external electric fields. The simulations reveal self-alignment, pattern conformation and the reduction of feature size in multilayer systems. A novel approach of transporting molecules on a substrate surface by reconfigurable molecular vehicles and embedded electrodes is proposed.

A Combined Ink Jet Printing/Photo-reduction Process for the Fabrication of μm-size Conductive Tracks

Ink jet printing is a promising process for the production of cheap, flexible electronic circuits. Miniaturisation of such circuits to sizes smaller than currently attainable by conventional ink jet printing would present benefits in terms of performance, economics and the environment. Two laser-based techniques (selective laser ablation and photo-reduction) used in conjunction with ink jet printing to reduce feature size are demonstrated. Selective laser ablation of metallic silver tracks enabled feature sizes to be reduced to ∼5 μm, with good edge definition and little damage to glass substrates. Photo-reduction of organometallic silver salt deposits enabled features down to ∼10 μm, with no measurable heating of the substrate; enabling the use of a wide range of polymeric substrates. Both techniques show potential for reducing the feature size of ink jet printed deposits by an order of magnitude on flexible substrates.

Sequential Stretching Lithography

ABSTRACTWe developed an embossing/imprinting based nanofabrication technique, dubbed Sequential Stretching Lithography (SSL). In this process, a master pattern is imprinted into an elastomer containing a film of uncured elastomer. The elastomer is cured and then elongated to increase feature density and reduce feature size. Replication of this substrate yields a new master that can be used in further reduction steps. One-dimensional grating features with a pitch size below 200 nm were fabricated from 750 nm-pitch grating lines. This process gives us a faithful pattern miniaturization in all aspects and, as a result, a much effective control on density and dimension regulation.

Technology Decisions to Minimize 450-mm Wafer Size Transition Risk

About every ten years, the semiconductor industry has increased its wafer diameter size. This change, when coupled with device innovations such as transistor design improvements, new materials, and lithography feature size reductions, have enabled the semiconductor industry to reduce cost per function by /spl sim/30% each year over the past 30 years, while enabling factories to be highly productive. This paper outlines key factory attributes and technology decisions required to make the next wafer size conversion from 300to 450-mm wafers and provides a detailed examination of the factors that should be considered by integrated circuit (IC) makers, equipment suppliers, and consortia members as a team. We show a subset of these attributes that can be decided quickly, a list of attributes that need more analysis and discussion, and conclude with a vision of the capabilities that a 450-mm factory will have.

Single-event upset in highly scaled commercial silicon-on-insulator PowerPC microprocessors

Single-event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes and core voltages. The results are compared with results for similar devices with bulk substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collections depth is more than an order of magnitude smaller in the SOI devices. The scaling of the cross section with reduction of feature size and core voltage dependence for SOI microprocessors is discussed.

Broadening of the variance of the number of upsets in a read-cycle by MBUs

This work presents A technique for establishing the proportion of multiple bit upsets (MBUs) in single event effects (SEE) test results based on a more sophisticated analysis of existing trial data and not requiring a memory map. The technique is demonstrated and verified with reference to recent neutron SEE results in charge coupled devices, since multi-pixel events are plentiful in these data and the mean number of pixels per event can be independently established through image analysis. This technique is most easily applied when the fraction of MBUs is relatively large, so it is predicted to become increasingly important in the future, as feature size reduction is expected to increase the proportion of MBUs.

A simulation model to characterize the photolithography process of a semiconductor wafer fabrication

The pressures on semiconductor manufacturers due to cost considerations, rapid growth of process technology, quality constraints, feature size reduction, and increasingly complex products are requiring ever higher efficiency from manufacturing facilities. The complexity of manufacturing high capacity semiconductor devices means that it is impossible to analyze the process control parameters and the production configurations using traditional analytical models. There is, therefore, an increasing need for effective models of each manufacturing process, characterizing and analyzing the process in detail, allowing the effect of changes in the production environment on the process to be predicted. The photolithography process is one of the most complex processes in semiconductor manufacturing. Using state-of-the-art computer simulation and a structured modeling methodology a generic model of photolithography flexible manufacturing cells has been developed and used to mimic the actual performance of the tools. Comparison of the output from the model with data from the plant shows the quality of the model. This paper discusses the technique used to develop the simulation model and includes a details on the structured modeling approach employed to develop reusable generic model for optimizing photolithography process parameters.

The future of gold in electronics

Gold-based materials have been a mainstay of the electronics and semiconductor industry since the physics was just a laboratory curiosity. Gold is the workhorse material in wire bond, flip chip and off wafer interconnections due to its corrosion resistance, ability to form metallurgical bonds by soldering or cold welding, and ease of fabrication. As the electronics and semiconductor industries grew, so did the use, of gold in spite of the feature size reduction so elegantly demonstrated in Moore's law. However, several revolutions in the Silicon miracle are threatening gold's place as the material of choice. Although cost is always an issue, the limitations are associated with the chemistry of gold based alloys. Will gold remain? Emerging requirements of bioelectronics, photonics and power requirements in conventional device represent new opportunities for gold to shine. Additionally, as the world market demand for electronic, semiconducting, bio-electronic and photonic technology increases, given the right technology, gold still can provide value proposition.

Analog front ends for highly segmented detectors

The evolution of analog front end ASICs is being driven by the increasing interest in fine-grained detectors and by rapid reduction in transistor feature size. Existing and proposed 2D pad and pixel detectors are moving towards higher segmentation in order to increase position resolution and/or signal-to-noise ratio. As pixel density increases above 10 4 pixels/cm 2 , the power dissipation of the front-end ASIC becomes a serious constraint. We discuss the power-constrained noise optimization of ASIC front ends in scaled CMOS technology.

Ultra-Thin Resists for Advanced Lithography

The continuous reduction of feature sizes in integrated circuits (IC) is driving the development of advanced lithographic techniques that enable patterning of sub-100-nm features with good fidelity and process margins. Requirements for printing these sub-100-nm features includes tight control of critical dimensions (CD), line edge roughness, and resist profiles. Reduction in exposure wavelengths to 157 nm and extreme ultraviolet (EUV) is pushing the development of new families of resist systems and the use of thin imaging layers that overcome the high absorption by materials of 157-nm and EUV radiation. In addition, thin imaging techniques may provide benefits for low-k1 and high-NA lithography using 193-nm radiation. The use of ultra-thin resists (UTR) introduces new concerns for resist properties including the possibility for increased defectivity and the reduction in etch resistance. In this paper, we describe results of studies using ultra-thin resist integrations to build working devices. These investigations have shown that UTR are not inherently limited by defectivity, and working devices with high yield have been fabricated using UTR integrations on multiple levels.

Single-event upset in evolving commercial silicon-on-insulator microprocessor technologies

Single-event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes and core voltages. Multiple-bit upsets in registers and D-cache were measured and compared with single-bit upsets. Also, the scaling of the cross section with reduction of feature size for SOI microprocessors is discussed.

Crosslinking and decomposition reactions of epoxide‐functionalized polynorbornene. II. Impact of reactions on mechanical properties

AbstractLow dielectric constant materials are critical to meeting the demand for continual reduction in feature sizes and increase in interconnect density required for future high‐speed microelectronic devices. Polymers based on functionalized norbornenes are inherently attractive for these applications as they exhibit good electrical properties such as a low dielectric constant and appealing mechanical properties. Although polynorbornenes inherently possess properties that are attractive for microelectronics packaging, films of these polymers are not solvent‐resistant. Solvent‐resistant crosslinked films can be attained by generation of acid species to promote cationic crosslinking of epoxide side groups. This article is the second part of a two‐part study investigating the crosslinking of a copolymer of decyl norbornene and epoxide norbornene. In the first part of this study, it was proposed that epoxide decomposition reactions are also possible at cure temperatures greater than 160°C. This decomposition mechanism results in the complete loss of crosslinkable epoxide groups while leaving the norbornene backbone intact. Although crosslinking and decomposition reactions have independent mechanisms, both reactions directly affect the level of crosslinking. In this part of the study, the solvent swelling behavior, tensile modulus, elongation to break, and residual stress were investigated for polymer films cured under various conditions to validate the proposed mechanisms. The trends observed with these properties are consistent with the counteracting nature of epoxide crosslinking and decomposition reactions. © 2003 Wiley Periodicals, Inc. J Appl Polym Sci 91: 1020–1029, 2004

Performance constraints for onchip optical interconnects

This work aims at defining the marks that optoelectronic solutions will have to beat for replacing electric interconnects at chip level. We first simulate the electric response of future electrical interconnects considering the reduction of the CMOS feature size /spl lambda/ from 0.7 to 0.05 μm. We also consider the architectural evolution of chips to analyze the latency issues. We conclude that: 1) it does not seem necessary in the future chips to consider the integration of optical interconnects (OIs) over distances shorter than 1000-2000 /spl lambda/, because the performance of electric interconnects is sufficient; 2) the penetration of OIs over distances longer than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> /spl lambda/ could be envisaged (on the sole basis of the performance limitation) provided that it will be possible to demonstrate new generations of (cheap and CMOS-compatible) low-threshold high-efficiency vertical cavity surface emitting lasers (VCSELs) and ultrafast high-efficiency photodiodes; 3) the first possible application of onchip OIs is likely not for interblock communication but for clock distribution as the energy constraints (imposed by the evolution of CMOS technology) are weaker and because the clock tree is an extremely long interconnect.

Applications of laser-generated surface acoustic waves for copper film process monitoring in integrated circuit industry (abstract)

We describe applications of a compact commercial instrument for laser generation and detection of surface acoustic waves (SAWs) to problems in metal film process control for the integrated circuit (IC) industry. [M. Gostein, M. Banet, M. Joffe, A. A. Maznev, R. Sacco, J. A. Rogers, and K. A. Nelson, in Handbook of Silicon Semiconductor Metrology, edited by A. C. Diebold (Marcel Dekker, New York, 2001)] The IC industry is undergoing dramatic changes with the continued drive to reduce feature size and increase circuit speed. One of the most important of these changes is the industry-wide move to replace circuit interconnect processes based on aluminum metallization with copper-based processes. The unique process challenges of copper metallization, coupled with the increasing cost of IC manufacturing in general, have resulted in an increased need for metal film thickness measurement for process control. Laser-generated and detected surface acoustic waves provide an ideal method for nondestructively measuring film thickness on product wafers as they move through an IC factory. A patented version of the technique has been incorporated into a commercial high-throughput measurement station. The measurement station analyzes specialized test structures in the scribe lines in between IC chips on a product wafer. Here, we describe application of the technique to all stages of the copper metallization process, including measurement of seed-layer copper and its associated underlying barrier metals, measurement of electroplated copper deposited atop the seed layer, and measurement of remaining copper film thickness following a chemical–mechanical polishing step. We highlight special capabilities to measure test arrays of submicron metal lines that closely resemble actual circuit elements. In addition, we discuss characterization of the elastic properties of typical and emerging thin film materials used in the semiconductor industry, which is a necessary step in setting up the SAW instrument for measurements on IC film stacks.