Abstract
The evolution of analog front end ASICs is being driven by the increasing interest in fine-grained detectors and by rapid reduction in transistor feature size. Existing and proposed 2D pad and pixel detectors are moving towards higher segmentation in order to increase position resolution and/or signal-to-noise ratio. As pixel density increases above 10 4 pixels/cm 2 , the power dissipation of the front-end ASIC becomes a serious constraint. We discuss the power-constrained noise optimization of ASIC front ends in scaled CMOS technology.
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