Circuit Size Reduction Research Articles

Design of Compact Bandpass Filters Using Quarter-Mode and Eighth-Mode SIW Cavities

The contribution of this paper is to propose novel balanced and dual-band bandpass filters (BPFs), using quarter-mode (QM) and eighth-mode (EM) substrate integrated waveguide (SIW) cavities, for the size reduction of the overall circuit. Two balanced BPFs, which separately demonstrate a third-order Chebyshev response and a fourth-order quasi-elliptic response, are realized by properly choosing, feeding, and coupling those QMSIW and EMSIW cavities. Not only desired differential-mode operation within the passband, but also good common-mode suppression in a certain frequency range have been achieved. Furthermore, a dual-band BPF with improved out-of-band rejection is also realized by properly constructing the coupling topology of four EMSIW cavities. An additional source-to-load coupling path is introduced in this dual-band BPF to obtain more transmission zeros (TZs). The sizes of resonant cavities utilized in the above designs are only one-fourth or one-eighth of those rectangular ones in conventional designs, which lead to a significant reduction in the overall circuit size. All proposed designs have been fabricated and measured to verify simulation predictions. Based on the author’s knowledge, it is the first time using QMSIW and EMSIW for balanced filter designs, and dual-band filter designs with TZs.

Unequal Divider with Asymmetric Shunt Open Stub for Reduced Size and Harmonic Suppression

This study presents an unequal divider with asymmetric shunt open stubs to reduce circuit size and achieve harmonic suppression. The design method was derived from S- to admittance parameter conversion of unequal divider. We validated the use of the parameter conversion method to reduce the size and achieve harmonic suppression of the unequal divider by implementing the divider at a power ratio of 3 at a center frequency of 1 GHz. The measured characteristics agreed well with the results of the calculation and the harmonic suppression was improved by more than 14 dB between the 2^nd and 4^th harmonics with 20% reduction in size compared to a conventional divider.

Miniaturized rat‐race coupler with tunable power dividing ratio based on open‐ and short‐circuited transdirectional coupled lines

ABSTRACTA miniaturized rat‐race coupler with a tunable power dividing ratio is proposed by using the open‐ and short‐circuited transdirectional coupled lines, design equations of which are derived to obtain perfect matching and isolation regardless of the coupling power. Based on the design equations, a microstrip rat‐race coupler with circuit size of λg/4 × λg/31 is implemented. Simulated and measured results are given to verify the proposed method. Compared with the existing tunable rat‐race coupler, the proposed coupler has 40–71% reduction of circuit size and a wide adjustable range of power‐dividing ratios (−10–13 dB) with a control voltage ranging from 3 to 12 V. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:2683–2689, 2016

A high‐efficiency gan power amplifier with harmonic control based on Si‐IPDS

ABSTRACTThis article presents a high‐efficiency power amplifier using quasi‐MMIC technology. The efficiency enhancement is achieved based upon the second or third harmonic control provided by input and output matching networks. The gate‐source voltage waveform control with Class‐F operation achieves significant efficiency improvements. The quasi‐MMIC technology using silicon‐integrated passive devices (Si‐IPDs) can drive the solution to provide compact size at 2.4 GHz. The output matching network for Class‐F operation is described, using lumped elements to reduce circuit size. The dimensions of the fabricated power amplifier are 3.6 mm × 7.6 mm, with a thickness of 0.15 mm. The measured results show that the power amplifier has a small signal gain of about 10 dB and a Psat of 41.8 dBm with a maximum drain efficiency of 70.8% at 2.4 GHz. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:2178–2182, 2016

Analytical Clustering Score with Application to Postplacement Register Clustering

Circuit clustering is usually done through discrete optimizations to enable circuit size reduction or design-specific cluster formation. In this article, we are interested in the register-clustering technique for clock-power reduction by leveraging new opportunities introduced by multibit flip-flop (MBFF). Currently, INTEGRA is the only existing postplacement MBFF clustering optimizer with a subquadratic time complexity. However, it severely degrades the wirelength, especially for realistic designs, which may nullify the benefits of MBFF clustering. In contrast, we formulate an analytical clustering score with a nonlinear programming framework, in which the wirelength objective can be seamlessly integrated and the solver has empirical subquadratic time complexity. With the MBFF library, the application of our analytical clustering method achieves comparable clock power to the state-of-the-art techniques, but further reduces the wirelength by about 25%. Even without the MBFF library, we can still achieve 30% clock wirelength reduction. In addition, the proposed method can potentially be integrated into an in-placement MBFF clustering solver and be applied to other problems that require formulating clustering scores in their objective functions.

6–18 GHz, 8.1 W size‐efficient GaN distributed amplifier MMIC

A 6–18 GHz, 8.1 W gallium nitride (GaN) distributed amplifier (DA) monolithic microwave integrated circuit (MMIC) is presented with compact size. To accomplish high-output power density with compact size, the last two sections of the DA consist of small-sized FETs. This approach improves the output return loss and allows the drain line lengths to be reduced thereby increasing the drain cut-off frequency and reducing circuit size, which results in increased gain and output power characteristics up to higher frequencies. Source via holes of GaN high electron mobility transistors (HEMTs) are also shared to reduce chip size. The proposed DA is implemented as a two-stage DA using a commercial 0.25 µm GaN MMIC process. It shows 8.1 W average continuous wave output power and 6.8 dB average associated gain from 6 to 18 GHz under 36 V drain bias with 6.7 mm2 chip area. The proposed DA obtains 1.21 W/mm2 output power density and 1.02 dB/mm2 gain density.

COMPACT MULTILAYER HYBRID COUPLER BASED ON SIZE REDUCTION METHODS

This paper presents a compact multilayer hybrid coupler based on a microstrip via- transition and short transmission line with a capacitor on each side to reduce circuit size. The microstrip via-transition is connected to two microstrip lines in different layers to configure a sandwich structure. To reduce the passive component circuit size, the design method uses a microstrip via-transition and a short transmission line with capacitors on each side. To validate the microstrip via-transition and short transmission line with capacitor, a multilayer hybrid coupler is implemented at a center frequency of 2 GHz. The measured characteristics agreed well with the simulation results, and above 90% circuit-size reduction compared with conventional couplers was realized.

Compact Wake-Up Module Design Based on an Energy-Harvesting Rectenna for Wireless Sensor Receivers

A new compact energy-harvesting module is proposed with compact design techniques. The rectifying circuit eliminates the band-pass filter and matching circuit, based on an active antenna concept and a direct matching technique. For exact circuit impedance, via holes are processed with precise fabrication techniques. The implemented circuit has achieved a circuit size reduction of 76.7%. The proposed system has been applied to a wireless wake-up receiver system with excellent operating performance.

A compact balun-diplexer using interdigital line resonators

A novel compact balun-diplexer applying new interdigital line resonators (ILRs) is presented in this article. It is found that the proposed ILR can not only reduce circuit size and but also realize high common mode rejection in differential mode operation frequency. By properly converting the symmetric four-port balanced bandpass filter (BPF) to a three-port device, a balun BPF with high selectivity and compact size are accomplished using ILRs. Then, the balun-diplexer can be realized by combining two well-designed balun filters with two 50 Ω transmission lines. The demonstrated balun-diplexer with operation at 1.8 and 2.45 GHz have been designed, fabricated, and measured. Excellent performances have been observed. Specifically, 0.4 dB in-band amplitude error, 1.8 in-band phase error, more than 50 dB selectivity and 45 dB isolation are obtained. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:485–489, 2015.

Latest Advances on Design and Implementation of DSP Systems

New challenges for implementations and design methodologies have been introduced over the years and the trend seems to continue. More and more complex algorithms need to be implementedwith higher performance but with strict constraints on power consumption. There is need for improving the implementation techniques, design methodologies, and algorithmarchitecture optimizations to tackle the challenges in present signal and information processing systems. This special issue contains a selection of papers reporting the latest advances on design and implementation of signal processing systems. The topics span from circuit level architectures in memories and arithmetic to dynamic code generation and from application implementations on mobile devices or heterogeneous platforms. In their paper Improving the Reliability of MLC NAND Flash Memories through Adaptive Data Refresh and Error Control Coding, Yang, Chen, Mudge, and Chakrabarti propose a combination of data refresh policies and low cost error control coding (ECC) schemes to address the errors in multilevel cell (MLC) NAND Flash memories given application characteristics. It is shown that an appropriate choice of refresh interval and BCH based ECC scheme can minimize memory energy while satisfying the reliability constraint. Hardware implementation of associative memories based on message passing algorithms on sparse graphs is described in Algorithm and Architecture of Fully-Parallel Associative Memories Based on Sparse Clustered Networks by Jarollahi, Onizawa, Gripon, and Gross. Architectures are derived that eliminates the need for computationally-complex winner-take all circuits. This results in improvement in clock frequency by about a factor of 2 and a reduction in circuit size. A design space exploration is provided and hardware complexity of the FPGA implementations are described. Antao and Sousa propose an implementation of an arithmetic accelerator for modular arithmetic based on the residue number system (RNS) in their paper A Flexible Architecture for Modular Arithmetic Hardware Accelerators based on RNS. An architecture of processing elements connected as a ring is proposed. The architecture is fully-parallel and is scalable to different algorithms and operand sizes. Implementations on FPGAs are provided. A Real-time Scalable Object Detection System using LowPower HOG Accelerator VLSI by Takagi, Tanaka, Izumi, Kawaguchi, and Yoshimoto proposes a real-time object detection system using a Histogram of Oriented Gradients (HOG) feature extraction accelerator and reconfigurable multiplyaccumulate array for supporting processing objects of different shapes. The proposed approach uses support vector machine for early classification. The system has been implemented on a 65 nmCMOS technology and the characteristics of the chip are reported in the paper. Blake and Hunter propose dynamically generated code for fast Fourier transforms. The fastest Fourier Transform in the South (FFTS) is a discrete Fourier transform library for x86 and ARM based devices, which was shown to be faster than FFTW, Intel IPP and Apple vDSP partly due to the use of program specialization and dynamic code generation. In this work, FFTS has been modified to dynamically exploit streaming store instructions on x86 machines, resulting in speedups of over 10 %, Also, when dynamic code generation is prohibited on some mobile platforms, FFTS has been altered to avoid it, while maximizing the performance. In paper Computer Vision Accelerators for Mobile Systems based on OpenCL GPGPU Co-Processing, Wang, Xiong, W. J. Gross (*) Department of Electrical and Computer Engineering, McGill University, Montreal, Quebec, Canada e-mail: warren.gross@mcgill.ca

Effects of a multimodality blood conservation schema toward improvement of intraoperative hemoglobin levels and off-pump transfusions in coronary artery bypass graft surgery.

Cardiothoracic surgery places significant demands on blood bank resources. Measures aimed at reducing intraoperative hemodilution were initiated as part of a blood conservation program. We initiated a series of measures aimed at reducing hemodilution volume: 1) reduction of intravenous fluid (IVF) volume, 2) reduction of circuit size, and 3) use of autologous priming techniques. All sources and volumes of IVF were obtained from the medical record. Intraoperative hematocrit (Hct) measurements were performed at the following intervals: first in operating room (OR), lowest on-pump, last on-pump, after protamine reversal, and immediately before discharge from OR. Red blood cell (RBC) transfusions were recorded. Intraoperative IVF, Hct levels, and transfusions were analyzed by cardiopulmonary bypass phase (prepump, on-pump, and off-pump), comparing preimplementation and postimplementation periods. Total intraoperative IVF volume was reduced by 973.7 mL (95% confidence interval, 671.6-1275.9 mL; p < 0.001) leading to a mean on-pump Hct improvement of more than 2% (p < 0.004). This contributed to a reduction in off-pump RBC transfusions by 20.6% (p = 0.014). A significant degree of heterogeneity in transfusion practice was noted between anesthesiologists. Blood conservation efforts in cardiac surgery should include efforts aimed at reducing hemodilution. Potential improvements are blunted by variation in transfusion practice.

Miniature quad‐band bandpass filter with passband individually controllable using folded SIR

A novel quad-band bandpass filter with individually controllable centre frequencies and bandwidths using a folded stepped-impedance resonator (SIR) is proposed. The new filter that centres at 2.4, 3.3, 4.1 and 5.2 GHz has a measured passband insertion loss of no more than 1.6 dB, and has a miniature circuit size of 0.448 λ g × 0.027 λ g . The presented filter is fabricated and tested, and the experiment demonstrates the new design. The new quad-band bandpass filter has compact and simple circuit topology, good performance of low passband insertion loss and transmission zeros, and greatly reduced circuit size compared with the relative reports.

Transversal Signal Interaction: Overview of High-Performance Wideband Bandpass Filters

This article presents an introduction of recently wideband bandpass filters based on transversal signal interaction concepts. Different resonant structures are reported on, including branch-line coupler/ring resonator, interdigital coupled lines, DSPSL 180° phase-shifting structure, Marchand balun, open/shorted coupled lines, T-shaped structures, and open/shorted stubs. Detailed comparisons of out-of-band transmission zeros, effective circuit size, 3-dB bandwidth, upper stopband, and group delay for the wideband/UWB filters discussed in this article are presented. Different bandwidth of wideband bandpass filters can be realized based on transversal signal interaction concepts, branch-line coupler/ring resonator can be easy to realize wide bandwidth with narrow upper stopbands due to their harmonic response. The filter structures using different 180° phase-shifting structures such as DSPSL, shorted coupled lines, and Marchand balun can meet UWB bandwidth/band demand, and the circuit size can be further reduced, while the selectivity and upper stopband should be further improved. The integrated applications of shorted/open coupled lines and shorted/open stubs can increase the numbers of the transmission zeros out-of-band, besides the circuit size reduction, the upper stopband can be also extended to over 4.7 f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> . Moreover, the transversal signal-interaction concepts have been also extended to the design of differential wideband//UWB balanced bandpass filters with broadband common-mode suppression in our former works.

A Miniaturize Bandpass Filter with Harmonic Suppression Using Meandered Quarter-Wavelength Resonators

A miniaturized bandpass filter with harmonics suppression is presented. The proposed filter consists of two quarter-wavelength microstrip resonators, which are meandered for circuit size reduction. An interdigital capacitor, loading at zero-voltage point, is employed to provide the desired coupling between the resonators at operating frequency, whereas the coupling coefficient at the third harmonic is realized to be zero. Besides, the second and fourth harmonics are suppressed sinceλ/4 resonators are adopted. Benefiting from these properties, a miniaturized bandpass filter with the second, third, and fourth harmonics suppression was designed and implemented. The final measured and simulated results show good consistence with the theoretical counterparts.

Design of Microstrip Quasi-Elliptic Bandpass Filter with Upper Wide Stopband Using Quarter-Wavelength Stepped-Impedance Resonators

In this article, a miniaturized quasi-elliptic bandpass filter using four quarter-wavelength (λ/4) stepped-impedance resonators is presented. With a simple design method, the presence of spurious harmonics can be avoided without using an extra filter or stub elements. The λ/4 stepped-impedance resonators in the structure of the filter resulted in a wide stopband and reduced circuit size. The combination of resonators with the same fundamental frequency but different spurious frequencies improved the stopband bandwidth. The proposed filter has the center frequency at 2.02 GHz and a 3-dB fractional bandwidth of 17.5%. On the other hand, the proposed filter shows wide upper stopband with attenuation level better than −22.2 dB up to 13.86fo, where fo is the passband center frequency. The circuit has a simple structure and a compact size. The designed bandpass filter has been simulated, fabricated, and measured, and there is good agreement between the measured and simulated results.

A Simple Compact Microstrip Wideband Bandpass Filter

Two wideband bandpass filters with miniature size and wide stopband are proposed by using cascaded U-shaped resonators. The filters exhibit bandwidths of 31.1% and 28.8% at about 5.3GHz and 5.6GHz, respectively. Both designed filters have simple structures and compact sizes, wide passband, excellent out-band performance with wide lower and upper stopbands, and a pair of transmission zeros on both sides of passband. The new designs have evident circuit size reduction compared with relative reports. A wideband microstrip BPF is fabricated and measured, and the measurement exhibits good agreement with the prediction.

A Bandwidth Improved Broadband Compact Lumped-Element Balun With Tail Inductor

A novel broadband compact lumped-element balun with a tail inductor is proposed in this letter. The employment of tail inductor improves amplitude and phase balances for better broadband performance. Furthermore, compared with baluns utilizing conventional micro-strip approaches or second-order lattice topology, this proposed topology offers significant circuit size reduction. Theoretical analysis of the optimized tail inductor value is presented to improve operation bandwidth. The concept is realized and validated by a 2.45 GHz balun with surface mounted devices (SMD). The measured results illustrate an amplitude balance less than 0.5 dB and a phase balance less than ±6° in a 36.7% bandwidth. The insertion loss is around 3.6 dB while the return loss of the unbalance port is better than 15 dB in the whole working frequency range. The core circuit occupies only 2 mm × 2.5 mm limited by SMD size.

Vacuum Assist: Angel or Demon CON

Vacuum-assisted venous drainage (VAVD) to enhance venous return during cardiopulmonary bypass (CPB) was described as early as 1958 but was not widely used until the late 1990s. VAVD was initially used to facilitate the use of smaller cannulas with ministernotomy but was increasingly used to allow reduction in CPB circuit size while maintaining CPB flow rates. This innovation was made without planned consideration to CPB circuit design, most critically that of the venous reservoir. Clinical reports of prime reduction facilitated by VAVD in both adult and pediatric CPB were associated with reduced nadir hematocrit and rates of transfusion that encouraged the proliferation of VAVD in CPB. Concomitantly, investigators have reported both in vitro and in vivo significantly increased arterial emboli associated with the use of VAVD, mostly related to accelerated venous air entrainment. In vitro studies continue to confirm this association and likely underestimate the resulting embolic load as a result of flawed study design. While the evidence for VAVD is equivocal, our understanding of the clinical impact of gaseous microemboli in CPB is similarly limited, most likely confined to blood–brain barrier disruption. It is only after two decades that CPB component design is receiving serious attention in terms of air handling. The ethics of innovation in the field of CPB warrant careful consideration. The application of VAVD is not without consequence.

임의유전체 기판을 이용한 주파수 혼합기의 소형화

A size-reduced high frequency mixer designed by adopting artificial dielectric substrate is described in this work. The artificial dielectric substrate is composed by stacking the lower substrate in which a lot of metalized via-holes exist, and upper substrate on which microstrip lines are realized. The effective dielectric constant increases due to the inserted lots of via-holes, and this may be applied to size-reduction of high frequency circuits. In this work, in order to present an application example of size-reduction for active high frequency circuits using the artificial dielectric substrate, a 8GHz single gate mixer is miniaturized and measured. It is described that the basic circuit elements for mixers such as hybrid, low pass filter, and matching networks can be replaced by the artificial dielectric substrate for size-reduction. The final mixer has 55% of size compared to the normal one. The measured average conversion gain is around 3dB which is almost similar result as the normal circuit.

A Novel Miniaturized Bandpass Filter Using Interdigital-Coupled Spiral-Shaped Resonators

In this paper, we present a novel miniaturized bandpass filter with high-selectivity performance and compact topology. For circuit size reduction, a spiral-shaped resonator with three branches is developed and examined. By suitably combining the resonators as the interdigital form, a special coupling scheme, which simultaneously provides electric and magnetic couplings, can be obtained readily. To investigate the new coupling scheme, the equivalent-circuit model of the proposed filter is derived and the lumped parameters are extracted. It is found that two transmission zeros can be realized close to the passband edges, resulting in high skirt selectivity. Meanwhile, the interdigital combination of the coupled-resonator pair makes the filter structure more compact. To verify the presented concept, an experimental filter operating at 1 GHz is demonstrated. The active area of the filter is only 11.6mm x 11.6 mm (0.061λg x 0.061λg), where λg is the guided wavelength at the operating frequency.