Area Cost Reduction Research Articles

Low-area and accurate inner product and digital filters based on stochastic computing

The inner product is a key operation in various applications, such as signal processing and pattern recognition. Research has shown that this function, when implemented in stochastic computing (SC) domain, can result in significant reduction in area cost and power consumption compared to its equivalent counterpart in the conventional binary-encoded (BE) deterministic computing. However, existing designs of SC inner product are disadvantaged due to high BE-SC conversion circuits, hence high overall area cost. They also suffer from correlation-induced errors that affect their accuracy performance. In this work, we propose a novel inner product design method for the SC domain that has high accuracy, low area cost, and most importantly, the circuit is correlation-insensitive. Experimental results show that the proposed design on average reduces 85.7% of hardware footprint when compared to its equivalent BE counterpart. We show that it outperforms current state-of-the-art SC designs in terms of area savings, both in computation and conversion costs. Furthermore, it achieves better (or comparable) accuracy performance compared to existing works, especially in designs having large number of inputs with low stochastic number lengths. Moreover, SC FIR filter based on the proposed design method outperforms state-of-the-art SC filters in terms of area and accuracy.

Joint Algorithm-Architecture Optimization of CABAC

This paper uses joint algorithm and architecture design to enable high coding efficiency in conjunction with high processing speed and low area cost. Specifically, it presents several optimizations that can be performed on Context Adaptive Binary Arithmetic Coding (CABAC), a form of entropy coding used in H.264/AVC, to achieve the throughput necessary for real-time low power high definition video coding. The combination of syntax element partitions and interleaved entropy slices, referred to as Massively Parallel CABAC, increases the number of binary symbols that can be processed in a cycle. Subinterval reordering is used to reduce the cycle time required to process each binary symbol. Under common conditions using the JM12.0 software, the Massively Parallel CABAC, increases the bins per cycle by 2.7 to 32.8× at a cost of 0.25 to 6.84% coding loss compared with sequential single slice H.264/AVC CABAC. It also provides a 2× reduction in area cost, and reduces memory bandwidth. Subinterval reordering reduces the critical path delay by 14 to 22%, while modifications to context selection reduces the memory requirement by 67%. This work demonstrates that accounting for implementation cost during video coding algorithms design can enable higher processing speed and reduce hardware cost, while still delivering high coding efficiency in the next generation video coding standard.

Efficient pipelined architecture for competitive learning

This paper presents a novel pipelined architecture for competitive learning (CL). The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for reducing the computation time. In the architecture, a novel codeword swapping scheme is adopted so that neuron competitions for different training vectors can be operated concurrently. The neuron updating process is based on a hardware divider with simple table lookup operations. The divider performs finite precision calculations for area cost reduction at the expense of slight degradation in training performance. The CPU time of the NIOS processor executing the CL training with the proposed architecture as an accelerator is measured. Experimental results show that the NIOS processor with the proposed architecture as an accelerator can achieve up to a speedup of 254 over its software counterpart running on a general purpose processor Pentium IV without hardware support.

Guest Editorial: Special Issue on EUC 2007

Embedded and ubiquitous computing is an exciting new paradigm that provides computing and communication services all the time and everywhere. Its systems are now affecting every aspect of our life to the point that they are hidden inside various appliances. This emergence is a natural outcome of research and technological advances in embedded systems, pervasive computing and communications, wireless networks, mobile computing, distributed computing and agent technologies, etc. This special issue has collected best papers presented in the 2007 IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2007), held in Taipei, Taiwan, ROC. These papers present state of the art in the areas of real-time and embedded software, power-aware hardware management, network security, embedded compiler techniques, mobility and security in advanced wireless networks, and data crawling. Best papers in the EUC 2007 conference were invited for submission. All the invited papers had undergone an intensive review process. The Editor-in-Chief agreed with our recommendation of the acceptance of eleven high quality papers. The first four papers focus on software techniques in embedded and ubiquitous systems. The first paper, entitled “Task Scheduling for Context Minimization in Dynamically Reconfigurable Platforms”, by Nei-Chiung Perng et al. describes a real-time approach to reducing the number of FPGA configuration contexts in dynamic reconfigurable systems. The second paper, entitled “Real-Time Embedded Software Design for Mobile and Ubiquitous Systems” by Pao-Ann Hsiung et al., describes a component-based software architecture that supports automatic synthesis and verification, aiming at high software design productivity. The third paper, entitled “SIGMA system: A Multi-OS Environment for Embedded Systems”, by Wataru Kanda et al., introduces a virtualization technique to support multiple operating systems for multi-processor embedded architectures. The fourth paper, entitled “Compiling for Reduced Bit-Width Queue Processors” by Arquimedes Canedo et al., presents a compiler technique for generating compact codes for embedded processors. The next three papers are on hardware management for embedded and ubiquitous computing. The fifth paper in this special issue, entitled “Energy-Efficient Considerations on a Variable-Bitrate PCI-Express Device”, by Jian-Jia Chen et al., presents a dynamic power management (DPM) algorithm for variable-bitrate PCI devices for power saving. The sixth paper, entitled “Design and Synthesis of An Multiprocessor System-on-Chip Architecture for Real-Time Biomedical Signal Processing in Gamma Cameras”, by Kai Sun et al., discusses communication synthesis and areacost reduction for an MPSOC Gamma Camera. The seventh paper, entitled “Variable Length Pattern Matching for Hardware Network Intrusion Detection System”, by Chun Xue et al., presents a high-performance hardware-based network intrusion detection system. The last four papers are related to wireless-network applications. The eighth paper in this special issue, entitled “A Lightweight Authentication Protocol for Low-Cost RFID” by Hung-Yu Chien et al., proposes a lightweight L.-P. Chang (*) Department of Computer Science, National Chiao-Tung University, Hsin-Chu, Taiwan, Republic of China e-mail: lpchang@cs.nctu.edu.tw

Area and performance analysis of value predictors

Value predictors that predict the results of instructions before their execution, have been proposed to improve the instruction-level parallelism at the microarchitecture level. Value predictors are categorised into static and dynamic predictors according to the type of classification of the instructions. At the expense of performance improvement, however, value predictors require extra area cost. The authors analyse the area cost of all value predictors and propose an area cost reduction method for static predictors, which decreases the area cost by at least 35% with negligible performance degradation. In addition, the authors compare all value predictors in terms of performance and cost effectiveness to provide guidelines in selecting a suitable value predictor according to application. Simulation results lead to the conclusion that a dynamic predictor adopting the distributed classification method achieves the best performance improvement ratio, while the last predictor with the proposed area cost reduction method requires the minimum area cost and achieves the best cost effectiveness.

Using collectively-derived standards to evaluate individual performance: a cautionary note on clinical practice guidelines.

The purpose of this work is to demonstrate the problem of evaluating an individual physician's performance relative to practice guidelines which have typically been derived from group consensus or some measure of central tendency. It is argued that when evaluated against a set of criteria derived at the macro-level, an individual physician's performance may justifiably vary due to the patient characteristics or the evolving process of care. It is also argued that it is not necessarily true that costs are reduced when practice variation is reduced. The results indicate that there are cost reduction in areas not targeted by the guidelines, suggesting a possible 'spillover effect' due to the increased vigilance in monitoring provider performance. The results also provide some evidence of increased costs following a reduction in variation. Caution should be exercised when evaluating individual physician performance relative to guidelines established at the aggregate level. Acceptable individual physician performance should be judged within the upper and lower boundaries of the implicit distribution of physicians' performances from which the established guidelines generated.