Area and performance analysis of value predictors

Abstract

Value predictors that predict the results of instructions before their execution, have been proposed to improve the instruction-level parallelism at the microarchitecture level. Value predictors are categorised into static and dynamic predictors according to the type of classification of the instructions. At the expense of performance improvement, however, value predictors require extra area cost. The authors analyse the area cost of all value predictors and propose an area cost reduction method for static predictors, which decreases the area cost by at least 35% with negligible performance degradation. In addition, the authors compare all value predictors in terms of performance and cost effectiveness to provide guidelines in selecting a suitable value predictor according to application. Simulation results lead to the conclusion that a dynamic predictor adopting the distributed classification method achieves the best performance improvement ratio, while the last predictor with the proposed area cost reduction method requires the minimum area cost and achieves the best cost effectiveness.