Abstract
Connected components labeling is a commonly used procedure when performing image analysis and segmentation, as well as pattern recognition processing. The state-of-the-art approach, proposed by (S.-H. Yang et al., 2005), uses a parallel algorithm to achieve high speed operation. Based on it, an area and speed efficient VLSI architecture was designed. However, as the size of the input image increases, the area cost increases as well. This paper proposes an optimization for the method from (S.-H. Yang et al., 2005), achieving considerable area cost reduction, mainly when large images are considered. The area economy is accomplished by processing the input image in partitions of columns. This way, the higher the number of columns of the input image, the greater will be the area cost reduction.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
