Reduced Output Voltage Ripple Research Articles

Commutation strategy for reduced output voltage ripple in alternative cascaded boost converter

SummaryWith the rapid penetration of low‐voltage direct current (DC) generators such as photovoltaic panels and storage energy systems, the need for processing energy has propitiated the optimization of power electronics converters. Conventional topologies of power electronics converters have well‐known limitations, mainly due to the parasitic elements and finite commutation times, which do not allow for obtaining a sufficient voltage gain. The literature review has demonstrated that cascade topologies are suited to overcome these limitations. However, to provide a low‐ripple output voltage, they require high values of capacitances. This paper presents an alternative boost converter developed by cascading two power cells. The conventional configuration is slightly modified, producing an alternative power cell. Even though the number of elements is increased, following the suggested commutation strategy, the derived converter can substantially reduce the output voltage ripple. Therefore, capacitors of small value can be employed, avoiding using electrolytic capacitors with shorter life spans than their film counterparts. Besides, given the cascaded connection, the converter possesses a quadratic‐type gain since two independent commanding signals are applied. The different states of commutation are analyzed in depth, allowing the selection of an adequate commutation strategy, which gives the advantage of canceling the output voltage ripple. The mathematical model of the converter is presented and then validated via a scale‐lab prototype. The simulation results evidence the good dynamic performance of the control‐loop design by means of the frequency response analysis.

Output Voltage Response Improvement and Ripple Reduction Control for Input-Parallel Output-Parallel High-Power DC Supply

Output Voltage Response Improvement and Ripple Reduction Control for Input-Parallel Output-Parallel High-Power DC Supply

Direct Synthesis scheme based PID controller design for Boost Converter

This study's aim is to provide an introduction toa specific methodology for optimizing the design of a boost converter. The main goal of this optimization is to determine the best inductor and capacitor parameter values in order to reduce output voltage ripple, maximize efficiency, and minimize output voltage deviation. In addition, a PID control approach is employed to regulate the boost converter's output voltage using the Direct Synthesis tuning method. The simulation's outcomes indicate that the proposed approach significantly enhances the performance of the boost converter and attains maximum efficiency. This methodology and control strategy can be applied to various boost converter applications to achieve stable and optimal performance.

A Rectifier-fed DC-DC Boost Converter with Improved Voltage Conversion Ratio and Reduced Output Voltage Ripple

A Rectifier-fed DC-DC Boost Converter with Improved Voltage Conversion Ratio and Reduced Output Voltage Ripple

Optimization Improvement Using Pi Controller to Reach CCCV Method in Lead Acid Battery Load

Solar energy can produce electrical energy with the help of photovoltaics so as to produce sufficient or even excessive supply to the electrical load. Therefore, it is necessary to store electrical energy (battery) from the excess unused energy. However, in the process of charging the battery, it takes a long time to fully charge the battery capacity and damage often occurs due to excessive voltage used. This can reduce battery life. The characteristics of the battery need to be considered so that the charging process can be carried out in accordance with the required provisions. The existence of the CCCV method can speed up the battery charging process with a constant current of 20% of the nominal current of the lead acid battery. To avoid overvoltage, the constant voltage method can anticipate the occurrence of damage. Utilization CUK Converter as charging can reduce output voltage ripple. The PI control on the CUK Converter produces a constant voltage of 13.8 Volts and a constant current of 1.44 Ampere. The average error generated by this system is 0.14%.

Reduction of Output Voltage Ripple with Dc-Dc Conversion Using Ky Converter

Reduction of Output Voltage Ripple with Dc-Dc Conversion Using Ky Converter

Design of a LLC Resonant Converter for Powering a PEM Electrolyzer

This paper proposes the design of a LLC resonant converter to supply a proton exchange membrane (PEM) electrolyzer. The PEM requires a low voltage with high current, a reduced output voltage ripple, and an overdamped dynamic behavior of the converter to avoid voltage overshoots. The designed converter allows satisfying the design constraints, minimizing switching and reverse recovery losses; the efficiency is influenced mainly by the output rectifier's conduction losses.

Output Voltage Ripple Reduction in a Symmetric Multistage-Stacked Boost Architecture (MSBA) Converter

This article proposes a different operation mode in a recently proposed converter, the multistage-stacked boost architecture (MSBA) converter working under the symmetric operation mode. The operation mode of the converter is analyzed with a modified pulse width modulation (PWM) scheme, in which the switching function of transistors is obtained from an interleaved scheme. The results show that the modified PWM results in a similar operation of the converter, with a reduced output voltage ripple, without increasing the switching frequency. A mathematical model of the converter is provided, the output voltage ripple calculation is performed in the traditional, and the modified PWM scheme, simulation, and experimental results are provided to verify the operation mode and the obtained equations.

Exact Modeling of the Low Energy Storage Quadratic Boost Converter

The low energy storage quadratic boost converter (LES-QBC) was recently proposed as an advantageous topology in terms of reduced output voltage ripple and fast dynamic response, besides high power density and reduced energy storage. The topological configuration can be exploited mainly through a 180° phase shift between the controlled switch gate signals. Nevertheless, this feature imposes a relevant challenge in terms of modeling, since traditional averaging an ripple estimation techniques cannot provide an accurate approximation to the actual switching dynamics of the converter. Motivated by this issue, in this article, we provide a complete quantitative analysis of both the steady-state and dynamic behavior of the LES-QBC, giving a fine understanding of their operation in continuous conduction mode when a pulse width modulator is used. The voltage gain, ripple factor, and dynamic behavior are modeled considering parasitic resistances and a wide operation range for the input voltage and the load. The demonstrated performance corroborates the high value of the converter for several applications in the industry. Every theoretical prediction is fully validated via simulations and experimental results.

A High Voltage Gain Multiport Zeta-Zeta Converter for Renewable Energy Systems

In this paper, a zeta-zeta coupled non-isolated multiport converter is proposed and implemented. The new dc-dc multiport converter discussed here facilitates the access of two renewable energy sources in the input side and a single output. Zeta converter topology facilitates high voltage gain with a reduced output voltage ripple. Multiport converters have become very prominent in recent past due to the prevalent establishments of distributed energy resources. Therefore in research arena there is no literature evidence for Zeta –Zeta converters used in multiport converters. This research work emphasize on suggesting a Zeta-Zeta multiport converter with reduced number of switches. The proposed converter is simulated in MATLAB/ Simulink environment and is also realized as a hardware prototype. The voltage gain and efficiency of the proposed circuit is compared with its counterpart multiport topologies. The simulation and hardware results show that the proposed topology is having a clear edge on its counter parts in voltage gain and efficiency. The proposed converter indisputably assures the utmost use of renewable energy resources.

FPGA based design and implementation of power conditioning unit for fuel cell powered vehicle using adaptive vector reference control method

The output of renewable energy is the power of low voltage and high current rated designs. Due to the output voltage being too low it does not meet the required maximum voltage load requirements. Therefore, in order to meet the high voltage load, the required limit of the power converter (DC-DC) is used to increase the voltage to the maximum. . The DC output voltage from a renewable energy source is given as input to a DC-DC converter, and the output generated from the converter is used to drive a load. KY boost converter is one of the recently developed DC-DC converters to reduce output voltage ripple. It is suitable for operation in equipment to below low ripple conditions. The disadvantage of this converter is that the boost voltage is a very low design parameter. To obtain the desired boosted voltage, and also to reduce the output voltage ripple, an optimized algorithm is used. Compared with the existing Drosophila optimization technology, the proposed Adaptive Vector Reference Control (AVRC) Method has higher convergence characteristics and lower output ripple. The simulation results are verified by MATLAB simulation with hardware results. The hardware is developed using the Xilinx FPGAs SPARTAN 6A controller, which simplifies the XC3S500E development board prototype in addition to providing additional flexibility for further improvements. The results clearly show improved performance and validate the model.

Interleaved Landsman Converter Fed EV Battery Charger with Power Factor Correction

In this paper, an electric vehicle (EV) battery charger with interleaved Landsman converter (ILC) followed by a flyback converter, is designed and evaluated for improved power quality (PQ) charging of battery. A built-in wave-shaping is obtained at the charger front-end due to improved PQ characteristics of ILC. This PFC converter consists of two Landsman converter cells, which are designed in discontinuous conduction mode (DCM) to share the input and output currents. The current sharing at input results into lower input current ripple as well as peak current stress through the switch, is reduced. This, further improves the input current harmonics profile. Moreover, the reduced output voltage ripple gives reduced rms current in the output capacitor. A phase shift PWM scheme (PSPWM) is used for ILC and the duty cycle for the switches is selected below 50%. This allows the ripple cancellation at line and load sides. The interleaving at PFC stage as well as DCM based design ensures a low cost charging solution as compared to the conventional Landsman converter (CLC) based chargers in this power range. However, the flyback converter provides the current control during the charging of the battery in constant current (CC) and constant voltage (CV) regions. The harmonics spectrum of mains current follows the recommended PQ regulations over a range of varying line voltages and loadings.

Comparative Study of Discrete PI and PR Controls for Single-Phase UPS Inverter

This paper presents a comparative study of discrete proportional integral (PI) and proportional resonant (PR) current control for single-phase uninterruptible power supply (UPS) inverters. There is an increasing requirement for current and voltage-controlled UPS inverters with very low or zero steady-state error, improved transient response and lower total harmonic distortion (THD). The most promising type of current regulator for single-phase inverters is PR control because it can introduce an infinite gain at a selected resonance frequency such as the fundamental frequency to eliminate the steady-state error, which cannot be achieved by well-known proportional integral (PI) control. Note that PI control has limitations in terms of the steady-state magnitude and phase errors. In addition, PI control also has limited harmonic rejection capability, unlike the PR control, also can compensate for low-order harmonics. Imperfections in the current and voltage control scheme results in higher harmonic distortion of the output current and voltage. In this paper, performance of PR control parameters ($K_{p}$ , $K_{i}$ , and $\omega _{c}$ ) and filter parameters ($L_{f}$ and $C_{f}$ ) are optimally tuned to obtain a very low THD current with reduced output voltage ripple and steady-state error. The analysis, design and implementation of both PI and PR current control in single-phase UPS inverter applications through simulations and experiments are also presented in this paper. The performance of both of these control schemes are analyzed in terms of steady-state response, transient response, and level of current harmonics.

Offset Voltage and Output Voltage Ripple Reduction of an Operational Amplifier using Auto-zero Technique

Offset Voltage and Output Voltage Ripple Reduction of an Operational Amplifier using Auto-zero Technique

A Switched Capacitor Voltage Converter With Exponentially Sized Capacitor Banks for Wide Load Range

Modern Internet-of-Things (IoT) applications need voltage converters to efficiently supply power with a small active period at various load conditions. The energy losses in such voltage converters during transitions between sleep-active can be significant, especially when the converters deviate from their optimum load conditions. The proposed Switched Capacitor (SC) converter, fully integrated on chip, incorporates Split-Capacitor Charging (SCC) and Energy Recycling (ER) techniques to minimize the energy losses during the transitions. The converter consists of multiple capacitor banks and their size increases in a binary exponential fashion. It employs an LDO to support a wide range of output voltage levels and reduce output voltage ripple during energy recycling and Continuous phase. In addition, we introduce an efficient test circuit structure using an on-chip digital controller and reconfigurable load circuit. This test structure can eliminate the unwanted parasitic values and varying delays, which are commonly incurred in the conventional test structures of on-chip voltage converters with off-chip loads and external control signal generation. We implemented the proposed voltage converter with a complete on-chip test structure using a 0.13 $\mu {\mathrm{ m}}$ CMOS process. Measurement results demonstrate a maximum efficiency of 86.83 % for a load current of $11~\mu \text{A}$ . It also achieved an improvement of 64.44 % in energy efficiency over conventional voltage converters for a short active period.

Performance Analyses of DC- DC Converter with Controller for PV Application

The utility of electric power plays a major role in economic development of a country. However, the demand for electrical energy goes on increasing every day. In order to meet out the demand for electricity, Renewable Energy Source (RES) has been identified as the alternate for electricity generation. Among the various RES, PV system has added consideration throughout the world due to its easy accessibility, boundless nature and of low maintenance cost. Since the voltage obtained from PV is not suitable for high power applications, a DC/DC step up converter is introduced. This converter should have reduced output voltage ripple which is an important factor that influences the overall performance of PV system. Hence, this work studied about the different topology of converter suitable for PV systems to have a better efficiency.

Optimum Boundary Inductance Control Concerning Limited PF for a DCM Boost PFC Converter

The discontinuous conduction mode boost power factor correction converter features zero-current turn- on for the switch, no reverse recovery in diode, and constant frequency operation. With traditional constant duty ratio control, the power transfer in each switching cycle exhibits great difference during a half-line cycle. Consequently, the peak and root mean square values of the inductor current are large, the same goes for the switch and diode. This increases not only the current stress of the power components but also the conduction and switching turn- off loss, and lowers the efficiency of the converter. Introducing third and fifth harmonics into the input current and varying the duty cycle correspondingly can reduce the aforementioned power transfer difference, and provide huge space for the increment of boundary inductance as well. An optimum boundary inductance control concerning limited power factor (PF) is proposed in this paper. For the maximum boundary inductance of the converter within wide input voltage range, the optimum harmonics amounts are analyzed and figured out. The proposed method brings about efficiency improvement, output voltage ripple reduction, and PF increase as well, especially at high input voltages. A prototype has been built and the experimental results are presented to show the validity of the scheme.

추진장치 성능시험설비의 출력 전압 리플 저감 필터에 관한 연구

추진장치 성능시험설비는 추진 인버터와 모터의 조합인 시험체의 성능시험과 추진장치의 개발 또는 인증 단계에서 추진장치의 성능을 시험하고 검증하는 장비이다. 추진장치 성능시험설비는 교류전원설비에서 공급되는 교류를 변환하여 부하제어설비가 요구하는 직류전원을 제한된 범위 내에서 안정적으로 제어할 수 있어야 한다. 본 논문에서는 추진장치 성능시험설비의 동작 특성에 따른 출력전압 리플 신호의 크기를 분석하고, 이를 바탕으로 전압 리플 저감 필터의 설계 방법에 대하여 정립하고자 한다. 설계된 전압 리플 저감 필터는 컴퓨터 기반 시뮬레이션 결과와 실험을 통하여 검증한다.

A High-Frequency Three-Level Buck Converter With Real-Time Calibration and Wide Output Range for Fast-DVS

This paper presents a 50-MHz 5-V-input 3-W-output three-level buck converter. A real-time flying capacitor ( $C_{F}$ ) calibration is proposed to ensure a constant voltage of $V_{g}$ /2 across $C_{F}$ , which is highly dependent on various practical conditions, such as parasitic capacitance, time mismatches, or any loading circuits from $C_{F}$ . The calibration is essential to ensure the reliability and minimize the inductor current and output voltage ripple, thus maintaining the advantages of the three-level operation and further extending the system bandwidth without encountering sub-harmonic oscillation. The converter is fabricated in a UMC 65-nm process using standard 2.5-V I/O devices, and is able to handle a 5-V input voltage and provide a 0.6–4.2-V-wide output range. In the measurement, the voltage across $C_{F}$ is always calibrated to $V_{g}$ /2 under various conditions to release the voltage stress on the high- and low-side power transistors and $C_{F}$ , and to ensure reliability with up to 69% output voltage ripple reduction. A 90% peak efficiency and a 23–29-ns/V reference-tracking response are also observed.

A High-Efficiency Split–Merge Charge Pump for Solar Energy Harvesting

An energy-efficient charge pump (CP) for solar energy harvesting is presented. A multistep split–merge charge transfer operation is introduced to replace the traditional one-step charge transfer process. Theoretically, this method increases the amount of charge transferred by up to 26% while reducing the Joule heat power loss by up to 7%. A five-stage complementary split–merge CP was designed and fabricated in a 0.13- $\mu\text{m}$ CMOS process. Measured results show an averaged 15.2% improvement of power conversion efficiency and a 1/8-fold reduction of output voltage ripple.