Reduce Chip Area Research Articles

IoT-driven optimization of a NxN enhanced pipeline multiplier

As the Internet of Things (IoT) continues to evolve, the demand for efficient hardware solutions is crucial. The paper explores the significance of hardware multiplication in IoT devices and discusses the challenges and opportunities in implementing dedicated hardware accelerators for multiplication operations. It specifically focuses on a highly efficient NxN-bit folded pipeline multiplier designed using advanced 22 nm CMOS technology and a modified hierarchical design approach. This multiplier achieves remarkable performance enhancements by reducing critical path delay through pipelining, resulting in a three-fold increase in operational speed compared to conventional multipliers. Additionally, it consumes only 0.2 mW of power and reduces chip area consumption by over 28 %. The paper emphasizes the importance of minimizing computational latency and power consumption to enable IoT devices to execute complex algorithms with improved speed and resource utilization. It also addresses trade-offs, such as area overhead and design flexibility, associated with hardware multiplication. The insights provided contribute to ongoing efforts to optimize hardware components for IoT applications, fostering the development of more capable and responsive IoT ecosystems. The study presents a rapid and energy-efficient alternative for multiplication in digital hardware, addressing the need for high-performance and energy-efficient devices in the context of the IoT.

A 128 × 128 SPAD LiDAR sensor with column-parallel 25 ps resolution TA-ADCs

This paper presents a design of single photon avalanche diode (SPAD) light detection and ranging (LiDAR) sensor with 128 × 128 pixels and 128 column-parallel time-to-analog-merged-analog-to-digital converts (TA-ADCs). Unlike the conventional TAC-based SPAD LiDAR sensor, in which the TAC and ADC are separately implemented, we propose to merge the TAC and ADC by sharing their capacitors, thus avoiding the analog readout noise of TAC’s output buffer, improving the conversion rate, and reducing chip area. The reverse start-stop logic is employed to reduce the power of the TA-ADC. Fabricated in a 180 nm CMOS process, our prototype sensor exhibits a timing resolution of 25 ps, a DNL of +0.30/−0.77 LSB, an INL of +1.41/−2.20 LSB, and a total power consumption of 190 mW. A flash LiDAR system based on this sensor demonstrates the function of 2D/3D imaging with 128 × 128 resolution, 25 kHz inter-frame rate, and sub-centimeter ranging precision.

A wideband and low-power mm-wave variable-gain phase shifter based on a source-switching scheme

This article presents a low-power and wideband variable-gain phase shifter (VGPS) designed and simulated in a CMOS 65 nm technology. It introduces a source-switching scheme for designing a variable gain amplifier (SSVGA) characterized by invariant linearity, impedance, and phase characteristics, showcasing improved gain and bandwidth compared to conventional VGAs. The current-reuse and staggered-tuning techniques are used to reduce power consumption and extend the bandwidth, respectively. The proposed VGPS enables gain tuning without the need for an additional gain tuning block, resulting in reduced chip area and sidelobe levels in phased array radar systems. The proposed VGPS, with a 5-bit resolution, achieves a 3-dB bandwidth of 18 GHz (53.5–71.5 GHz) and exhibits RMS gain error range from 0.23 to 0.5 dB and RMS phase error range from 0.54° to 2.65° with phase calibration based on simulation results. It achieves a peak average gain of 1.2 dB at 58.5 GHz while consuming a DC power consumption of only 5 mW with a 1.2 V power supply voltage. Moreover, it demonstrates a wide gain tuning of 20.6 dB, allowing for flexible gain adjustments.

WITHDRAWN: Design of a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency, and high-speed

In this paper, we propose a hybrid full-swing adder (HFSA) circuit that uses the hybrid full-swing logic (HFSL) technique, which consists of 20 transistors. This circuit relies heavily on a 12-transistor XOR-XNOR circuit to optimize the area and power. Our novel XOR-XNOR circuit plays a crucial role in achieving high-efficiency HFSA circuits. It integrates 2-to-1 multiplexers, pass transistor logic, and inverters to deliver glitch-free full-swing outputs. We compared the efficiency and practicality of our design with those of 10 alternatives by considering their performances and characteristics. Our novel XOR-XNOR circuit surpassed its counterparts with an exceptional chip area reduction of 14.14–28.01 %, an average power of 2.44 μW, and remarkably low delays of 25.88 and 24.87 ps. Notably, the proposed full adder achieved a chip area reduction of 11.30–49.69 %, 3.582 μW power, and a 72.66 ps delay. It emphasizes large-scale structures, such as 4-bit to 64-bit full adders, implemented using cascaded designs with a novel ripple carry adder. Using multipoint and Monte Carlo analysis in the ADEXL design suite to ensure the reliability of all circuits using the Cadence Virtuoso with the GPDK45 nm technology. The proposed method is an alternative to high-speed electronic systems with potential benefits.

A high-efficiency burst mode boost converter with a sharing main power NMOS for start-up

This paper presents a high-efficiency boost converter with a wide input range and a start-up strategy of sharing main power NMOS which can start-up at an input voltage of 700 mV. A burst mode with boundary conduction mode (BMBCM) control is utilized in the proposed boost converter to achieve high efficiency across the wide input power range. A method is also suggested to determine the optimal peak inductor current for a given input range. Compared to other start-up strategies, the proposed start-up circuit reduces chip area by sharing the main power NMOS with the normal operation mode, eliminating the need for an additional start-up power transistor. A new ultra-low-power voltage detection circuit is used to control the start-up process. The proposed boost converter is designed and fabricated in a 180 nm BCD process with an active chip area of only 0.33 mm2. The circuit achieves a peak efficiency of 94.8% at an input voltage of 3 V and an output voltage of 3.6 V, while maintaining an efficiency of at least 65.9% across the input power range of 7 μW to 300 mW.

Compact Bandwidth-Enhanced 180-Degree Phase Shifter Using Edge-Coupled Multi-Microstrip and Artificial Transmission Line.

Compactness has obtained sufficient importance in wideband phase shifter design considerations, as it is directly related to fabrication cost. In this paper, a novel structure was presented to create compact broadband 180-degree phase shifter, which has the advantages of enhanced bandwidth and significantly reduced chip area. The proposed configuration consists of edge-coupled multi-microstrip lines (ECMML) and an artificial transmission line (ATL) with dual-shorted inductors, both of which have the periodic shunt load of capacitors. The ECMML can provide a high coupling coefficient, leading to an increase in the bandwidth, while the introduced capacitors can greatly reduce the line length (35.8% of the conventional method). To verify the relevant mechanisms, a wideband switched network with compact dimensions of 0.67 × 0.46 mm2 was designed via 0.15-micrometer GaAs pHEMT technology. Combined with the measured switch transistor, it was shown that the proposed phase shifter exhibits an insertion loss of less than 2 dB, a return loss of greater than 12 dB, a maximum phase error of less than 0.6° and a channel amplitude difference of less than 0.1 dB in the range of 10 to 20 GHz.

High performance quaternary logic designs using GNFETs

The implementations of quaternary circuit schematics are presented in this paper. The quaternary logic is a better choice over the conventional logics because it offers high operating speed, reduced chip area and reduced on-chip interconnects. A new method is presented to design quaternary schematics using graphene nanoribbon field effect transistors (GNFETs). The dimer line of graphene nanoribbon (GN) is used to control the threshold voltage of GNFETs. Four quaternary logic inverter circuits such as standard quaternary inverter (SQI), intermediate quaternary inverter (IQI), positive quaternary inverter (PQI) and negative quaternary inverter (NQI) along with the NAND and NOR circuits are proposed. Furthermore, the quaternary half adder circuit is designed that helps to develop complex designs. The HSPICE simulator is utilized for simulating the proposed designs to obtain the performances such as delay, power and power delay product (PDP). The obtained circuit performances are compared with carbon nanotube FETs (CNFETs) based circuits. The comparison results show that the proposed GNFET circuits achieved 53.51% of overall performance improvement over the CNFET circuits.

Optical neural ordinary differential equations.

Increasing the layer number of on-chip photonic neural networks (PNNs) is essential to improve its model performance. However, the successive cascading of network hidden layers results in larger integrated photonic chip areas. To address this issue, we propose the optical neural ordinary differential equations (ON-ODEs) architecture that parameterizes the continuous dynamics of hidden layers with optical ODE solvers. The ON-ODE comprises the PNNs followed by the photonic integrator and optical feedback loop, which can be configured to represent residual neural networks (ResNets) and implement the function of recurrent neural networks with effectively reduced chip area occupancy. For the interference-based optoelectronic nonlinear hidden layer, the numerical experiments demonstrate that the single hidden layer ON-ODE can achieve approximately the same accuracy as the two-layer optical ResNets in image classification tasks. In addition, the ON-ODE improves the model classification accuracy for the diffraction-based all-optical linear hidden layer. The time-dependent dynamics property of ON-ODE is further applied for trajectory prediction with high accuracy.

Approximating Arithmetic Circuits for IoT Devices Data Processing

Smart cities require improved and new generation IoT devices, sensors, and technology so that a whole new digital environment can be created. The various aspects of the smart city can be improved through digital transformation, sustainability, resource management, improved quality of life, and security because of emerging applications such as voice recognition, image sensing, and so on. There is a massive deployment of smart devices and sensors, which sense, collect, and process a large amount of data. So there are many critical strategies and intelligent computing is required. The most popular way to solve computational issues with conventional blocks and structures to achieve exact, deterministic results is hard computing. However, emerging applications are tolerant towards errors, so the need for a precise result is diminishing. Approximate computing is a new paradigm in the field where error tolerance is applicable; it relaxes the need for an accurate and deterministic result while also providing advantages in terms of area, time, and delay. In this paper, we proposed a novel approximate computation based on a systematic approach that utilises the Look-Up-Table (LUT) with specific errors to achieve an approximate arithmetic circuit. Approximate adder circuit is designed so that this technique can be reused for different designs deployed in various applications or IoT devices. The analysis is based on area, delay with a considered error percentage. The proposed arithmetic circuit achieves a 68 % reduction in chip area compared to the exact one with a delay of 6.159 ns. The results show that the designed approximate arithmetic circuit is smaller in size, and energy-efficient and can be exploited to implement circuits used in IoT devices.

Design of Ternary Logic Circuits using Pseudo N-type CNTFETs

In this paper, a novel method is presented to design ternary logic circuits for nanoelectronics applications. The ternary logic is a best alternative to the binary logic because it offers reduced interconnects, faster operating speed and reduced chip area. The digital logic circuit designs are developed using Pseudo N-type carbon nanotube field effect transistors (CNTFETs). The threshold voltage of CNTFETs is altered by the CNT diameter that is defined by the chirality vector. The ternary inverters such as standard inverter (SI), positive inverter (PI) and negative inverter (NI) and ternary basic gates such as AND, NAND, OR and NOR gates are designed. Furthermore, the half adder circuits developed which assists to develop complex circuit schematics. The proposed ternary schematics are designed and simulated using the HSPICE simulator. Moreover, the performance of the proposed circuits are investigated in terms of delay, power dissipation and power delay product (PDP) and compared with the existing circuits. It is observed that the proposed circuits show average performance improvement up to 47.48% over the existing circuits.

An Integrated Driver With Bang-Bang Dead-Time Control and Charge Sharing Bootstrap Circuit for GaN Synchronous Buck Converter

This article proposes a high-frequency integrated gate driver for gallium nitride (GaN) synchronous buck converter. The proposed adaptive bang-bang dead-time control minimizes dead-time at any load condition. Thus, it mitigates the excessive power loss caused by GaN device reverse conduction in high-frequency applications. The proposed charge sharing bootstrap circuit ensures sufficient gate overdrive voltage with reduced chip area. Fabricated in a TSMC 0.25- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m BCD process, the driver integrated circuit enabled GaN-based buck converter to operate at 10 MHz switching frequency with minimal dead-time to as low as 0.4 ns under light load and heavy load conditions. Compared with fixed dead-time control, the proposed work improves around 5% efficiency under heavy load condition. The fully integrated bootstrap circuit with 100 and 60 pF (HV) capacitor obtained the lower than 0.6 V driving voltage drop with only 45% capacitance and around half of the voltage drop compared with a conventional bootstrap circuit. Besides, the proposed driver successfully tackled the parasitic ringing and dead-time overcharging issues in the GaN converter.

A Broadband Fully Integrated Power Amplifier Using Waveform Shaping Multi-Resonance Harmonic Matching Network

In this article, we propose a broadband fully integrated power amplifier (PA) using a waveform shaping harmonic matching network. A comprehensive theory is developed for the proposed multi-resonance harmonic matching network to derive design criteria for achieving wide bandwidth, low insertion loss, and optimum load impedances in the second- and third-harmonic frequency bands. Furthermore, it is shown that this network can be realized using a lower total inductance compared to a standard bandpass network which is an important feature in reducing chip area and fabrication cost. A fully integrated PA prototype is implemented using a 250-nm GaN-on-SiC process with 28-V supply. The PA provides 33.9&#x2013;36.1dBm output power (at 2&#x2013;3dB gain compression), 42&#x2013;51&#x0025; drain efficiency (DE), 38&#x2013;48&#x0025; power-added efficiency (PAE), and 10&#x2013;12.2dB power gain, across 4.0&#x2013;6.0GHz. The output-power 1-dB bandwidth is 3.6&#x2013;5.6GHz (44.5&#x0025;). For a 64-QAM signal with 8dB peak-to-average power ratio (PAPR) at 5.0GHz, the PA can provide 30.2dBm average output power and 32&#x0025; average PAE with RMS error vector magnitude (EVM) of &#x2212;34.0/&#x2212;32.4/&#x2212;28.4dB (2.0/2.4/3.8&#x0025;) for 50/100/200MHz modulation bandwidth, without using digital predistortion (DPD). The maximum average output power and average PAE, under the linearity constraint EVM &#x003C;&#x2212;28dB, are respectively 32.1/32.0/30.2dBm and 39/38/32&#x0025;, for modulation bandwidth of 50/100/200 MHz.

Design of Multi-Valued Logic Circuit Using Carbon Nano Tube Field燭ransistors

The design of a three-input logic circuit using carbon nanotube field effect transistors (CNTFETs) is presented. Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices, which is why this design is so popular, and it also reduces chip area, both of which are examples of circuit overheads. The proposed module we have investigated is a triple-logic-based one, based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values, as well as comparisons of the design working with various load capacitances. Comparing the proposed design with the existing design, the delay times was reduced from 66.32 to 16.41 ps, i.e., a 75.26% reduction. However, the power dissipation was not optimized, and increased by 1.44% compared to the existing adder. The number of transistors was also reduced, and the product of power and delay (P*D) achieved a value of 0.0498053 fJ. An improvement at 1 V was also achieved. A load capacitance (fF) was measured at different values, and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps, with a range of 61.06 ps. The power dissipations ranged from a minimum of 3.38 µW to a maximum of 6.49 µW. Based on these results, the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.

A Single-Stage Dual-Output Regulating Rectifier With Hysteretic Current-Wave Modulation

This article presents a 6.78-MHz single-stage dual-output regulating rectifier for miniaturizing the true wireless devices. The proposed rectifier topology realizes ac-dc power conversion and dual-output voltage regulation simultaneously in one single stage, using only four on-chip power transistors, thereby reducing chip area and off-chip components and improving the system power conversion efficiency. We integrate high voltage (HV) and low voltage (LV) transistors in the proposed dual-output rectifier for HV and LV output voltages, respectively. The proposed two independent three-level current-wave modulation (CWM) controllers realize voltage conversion and regulation for each output independently, with the instant transient response and no cross-regulation problem. The proposed dual-output regulating rectifier, fabricated in 0.18- μm CMOS using 1.8-/3.3-V devices, can deliver a total maximum power of 1.02 W at the dual-output voltages of 1.8 and 3.3 V. The circuit achieves a measured peak efficiency of 91.9% with an instant load-transient response for a load current step between 20 and 200 mA. The cross-regulation between the dual-output voltages is unnoticeable.

4th order current-mode and transresistance-mode MOSFET-C low-pass filter for multi-standard receivers

This work presents a novel 4th order current-mode and transresistance-mode low-pass filter based on MOSFET-C architecture. Proposed filter's cut-off frequency can be easily adjusted from 15 MHz up to 45 MHz for the analog baseband filters used in multi-standard receivers. The main core circuit of the filter contains only 7 transistors in order to reduce chip area and power consumption. Also, the proposed 4th order architecture have dual outputs in different modes facilitating signal conversion and different signal operations. The proposed structure has (54.3 μm × 34.1 μm) chip area and post layout simulations are examined extensively to prove performance of the filter. Also, input referred noise (IRN) characteristics of the filter outputs are shown in order to overcome thermal noise effects worsening the performance of the filter. Power consumption changes from 195.8 μW up to 1.37 mW whereas cut-off frequency is varied from 15 MHz up to 45 MHz. Provided results show that the proposed filter scheme brings a promising opportunity to designers for the analog baseband operations in multi-standard communication receivers.

High gain and low noise wideband folded-switching mixer employing transformer and complimentary CS/CG hybrid topology

In this paper, a high gain and low noise wideband folded-switching down conversion mixer has been designed. A differential complimentary common source/common gate (CS/CG) hybrid topology is utilized as the input RF transconductor stage, where a transformer is subtly applied to the source nodes of the complimentary CS/CG transistors. With the transformer and complimentary CS/CG hybrid topology as the input RF transconductor for both RF signal amplification and chip area reduction, the conversion gain, noise figure, input impedance matching, and chip area-efficiency of the mixer can be signficantly improved. Under a 0.8 ​V supply voltage and 1 ​dBm LO power, the mixer exhibits a conversion gain of 12.2–17.9 ​dB and a double-sideband noise figure of 2.6–6.1 ​dB between RF frequencies from 3.0 to 7.0 ​GHz. The IIP3 is −6.5 ​dBm at the RF frequency of 5.0 ​GHz while consuming only 2.72 ​mW of power at an IF frequency of 100 ​MHz. The chip area is only 0.55 ​mm ​× ​0.65 ​mm.

Voltage Differencing Transconductance Amplifier based Ultra-Low Power, Universal Filters and Oscillators using 32 nm Carbon Nanotube Field Eff ect Transistor Technology

Carbon nanotube field effect transistor (CNTFET) is strong candidate to replace existing silicon based transistors. The ballistic transport of electrons in CNTFET channel leads to ultra-low power or high frequency devices. Since, lot of digital applications of CNCTFET were presented. However, much less work was done in analog applications of CNTFETs. This paper presents analog applications of CNTFET and CNTFET implementation of voltage differencing transconductance amplifier (VDTA). The CNTFET VDTA based filters and oscillators were proposed. The VDTA circuits are resistorless and can be tuned electronically only by changing transconductance. The proposed CNTFET VDTA show power consumption of 15000 times less than compared to 0.18um TSMC technology and significant reduction in chip area. All simulations were performed using HSPICE and MATLAB simulation tools.

Analytical Synthesis of High-Pass, Band-Pass and Low-Pass Biquadratic Filters and its Quadrature Oscillator Application Using Current-Feedback Operational Amplifiers

In this paper, a method of realizing voltage-mode (VM) non-inverting high-pass filter (HPF), band-pass filter (BPF), low-pass filter (LPF), and inverting low-pass filter (ILPF) transfer functions structure with two grounded capacitors and four resistors through an analytical synthesis method is presented. The synthesis structure of the VM biquadratic filter consists of a voltage proportional block and two voltage lossless integrators based on the use of current feedback operational amplifiers (CFOAs). It is demonstrated that the derived biquadratic filter structure can simultaneously realize VM HPF, BPF and ILPF transfer functions or VM BPF and LPF transfer functions at a high-input impedance terminal. The VM biquadratic filter can independently adjust the resonance angular frequency and quality factor. By slightly modifying the proposed biquadratic filter, a VM quadrature sinusoidal oscillator can be achieved. The proposed biquadratic filter and quadrature oscillator have been simulated by OrCAD PSpice and appropriate hardware has been implemented with AD844-type CFOAs. In order to reduce power consumption, reduce chip area, reduce costs, and improve system integration, integrated VM CFOA-based biquadratic filter circuits and quadrature oscillator circuits are very important. The proposed filter and quadrature oscillator have been further fabricated in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> 1P6M CMOS process technology. The entire chip area is 0.974 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , including a filter chip cell and an oscillator chip cell. Under the supply voltage of ±0.9 V, the total power dissipation of the filter chip cell is 5.4 mW, and the figure-of-merit (FOM) of filter chip cell is 66.7%. The measured value of the third-order intermodulation distortion of the filter chip cell is −55.29 dBc and the third-order intercept point is 19.9 dBm. The measured phase noise of CFOA-based filter chip cell at 1 kHz offset is less than −99.76 dBc/Hz.

A Predistortion-Less Digital Transmitter With −50-dB ACLR Exploiting Output Conductance Linearization

Switched capacitor power amplifiers (SCPAs) are a class of digital transmitters which have shown promising results for high linearity with good drain efficiency (DE). Their linearity is limited by AM-PM distortion, caused by a difference in output conductance in switching and nonswitching driver cells. Often, digital predistortion (DPD) is required to transmit higher-order modulation schemes. In this letter, a driver cell implementation as an inverter with drain resistors is proposed which has equal output conductance in both cases, aiming to eliminate AM-PM distortion. An SCPA with these driver cells is implemented in a 22-nm fully depleted silicon-on-insulator (FD-SOI) CMOS process which demonstrates excellent DPD-less linearity with an adjacent channel leakage ratio (ACLR) of −50 dB and an error vector magnitude (EVM) of −45.5 dB for 5-MHz 1024 QAM signals at a DE of 8.8%. A matching network exploiting bondwires as high-Q inductors removes on-chip inductors and significantly reduces chip area.

A Fast Switching Current Controlled DC/DC Converter for Automotive Applications

Automotive industry requires integrated circuits with both low cost, to maintain product competitiveness, and high efficiency, moving towards solutions as green as possible. Each electronic device within the car needs for a regulator to provide a steady supply to ensure correct and safe operation. Among all regulator, DC/DC Converters are the most valid solution to achieve a high efficiency-price ratio. The DC/DC Converter needs for a control loop to monitor the load operation. The basic control loop topologies are well known in the state-of-the-art. The paper presents a DC/DC Buck Converter for automotive applications designed in low cost technology with an upgraded version of the Peak Current Mode Control which uses a constant off-time. For chip area reduction, an n-channel power-DMOS is chosen as power transistor. The design of each block composing the circuit is presented. To guarantee DC-DC Buck converters high-efficiency and low cost (in terms of external components) increasing switching frequency is mandatory. A  1.5 MHz switching frequency has been chosen to reduce external components size. The device is optimized by design to be able to achieve 94.4% efficiency using a 3V  3A load. The post-layout simulations of the system are shown, confirming the expected circuit behavior also including the presence of wiring parasites. A PCB is also designed to test the packaged die to ultimately demonstrate the chip’s robustness and suitability in a real automotive application.