Reduction In Capacitor Size Research Articles

Capacitor sizing of three‐level neutral point clamped voltage source inverter for electric vehicles: Effects of modulation and motor characteristics

AbstractA three‐level neutral point clamped (3L‐NPC) voltage source inverter (VSI) topology can be advantageous in electric vehicles with a high DC‐link voltage and a high switching frequency. A bulky DC‐link capacitor is not an option; thus, the DC‐link capacitor's sizing considering the traction system characteristics is an important design step. This paper investigates how the DC‐link capacitor size of a 3L‐NPC VSI gets affected by the combination of the interdependent characteristics of an electric drive, such as its power factor, modulation index, current, and fundamental frequency, with the effects of the modulation methods. Five pulse width modulation (PWM) methods, of which three of them have an active neutral point potential control, are compared in terms of their neutral point potential (NPP) oscillations. Then, the size of the DC‐link capacitor is determined for each PWM method so that the NPP ripple is kept under desired limits at all operating conditions. It is shown that both the modulation technique and the electric machine characteristics influence the capacitor size. For example, electric machine design modifications can introduce more than a 30% reduction in capacitor size. Finally, DC‐link and NPP oscillations with different PWM methods are experimentally validated in a scaled‐down 3L‐NPC inverter.

A multi‐port MMC topology with reduced capacitor size for use in grid‐connected PV systems

AbstractIn this article, a novel multi‐port modular multilevel inverter topology is presented for grid‐connected photovoltaic systems, which feature a smaller capacitor size compared with its counterparts. In the proposed MMC topology, each submodule is an individual input port being fed by an independent PV array through a boost converter. This allows modularity of the proposed topology, easing its maintenance and facilitating its expansion for PV integration. Individual maximum power point tracking controllers are used to operate the boost converters in each submodule to extract maximum energy from their PV arrays under different radiation conditions. A model‐predictive control scheme is designed for regulating the proposed multi‐port MMC topology to inject the harvested solar power to the grid. This controller enables minimized circulating currents in the MMC arms and balanced capacitor voltages in the MMC submodules, while total harmonic distortion (THD) of injected current to the grid is kept within the limits. The proposed multi‐port MMC topology with model‐predictive control is validated under different radiation conditions for a grid‐connected PV system to indicate that the proposed topology has a desirable performance under different radiation conditions.

Capacitor Size Reduction of Multilevel Inverters by Utilizing Neutral Shifting

Reduction of size of capacitor is an active area of research as it greatly reduces cost and footprint of the system. A level doubling network (LDN) is a half-bridge with floating capacitor in its dc bus, which doubles the number of ac output voltage levels when connected to a multilevel inverter unit. LDN automatically gets settled at a desired voltage level without closed-loop control. Capacitor of the LDN gets charged for a complete half cycle and discharges for the next half-cycle and therefore results in a higher ripple voltage demanding a higher capacitance. This paper presents a new method to reduce the size of LDN capacitor keeping the voltage ripple within limits. This is achieved by shifting the Neutral point of inverter between positive and negative dc busses of the LDN, which enables the capacitor to charge or discharge more frequently, irrespective of the modulation index and load power factor. In addition, controlling is done in such a way that uniform power distribution ratio among the cells of a single phase leg of the inverter is achieved. Working principle of the proposed method is verified through simulation in MATLAB/Simulink and experimentation on a laboratory prototype.

A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters

A 12-bit 104 MS/s successive approximation register analog-to-digital converter (SAR ADC) is developed for a digitally-assisted wireless transmitter system for use in cellular applications. A power-on calibration method is implemented to correct capacitor DAC mismatch and reduce capacitor size, thereby lowering the current consumption of the input buffer and reference generator. The total capacitor size is reduced to 0.6 pF, from the 3.6 pF required for 12-bit matching. The ADC analog core area is 0.003 mm2. The proposed method achieves 88 dB SFDR at 26 MHz sampling rate and 76.2 dB SFDR at 104 MHz sampling rate after calibration. The measured DNL and INL are 0.5 LSB and 1.1 LSB, respectively. The ADC achieves both high speed and low power by combining several features, namely digital calibration, redundancy, asynchronous bit-cycling, monotonic switching, 25% duty-cycle sampling period, 3 dB input gain, and a fully dynamic comparator. The power consumption from 1.2 V/1.1 V supplies is 0.88 mW for a single ADC core and 6.1 mW for the entire I/Q ADC, including the reference generator and input buffers. The ADC is fabricated in 28 nm CMOS.

Analysis and Design of a Modular Multilevel Converter With Trapezoidal Modulation for Medium and High Voltage DC-DC Transformers

Conventional dual-active bridge topologies provide galvanic isolation and soft-switching over a reasonable operating range without dedicated resonant circuits. However, scaling the two-level dual-active bridge to higher dc voltage levels is impeded by several challenges among which the high dv/dt stress on the coupling transformer insulation. Gating and thermal characteristics of series switch arrays add to the limitations. To avoid the use of standard bulky modular multilevel bridges, this paper analyzes an alternative modulation technique, where staircase approximated trapezoidal voltage waveforms are produced; thus, alleviating developed dv/dt stresses. Modular design is realized by the utilization of half-bridge chopper cells. This way the analyzed dc-dc transformer employs modular multilevel converters operated in a new mode with minimal common-mode arm currents, as well as reduced capacitor size, hence reduced cell footprint. Suitable switching patterns are developed and various design and operation aspects are studied. Soft-switching characteristics will be shown to be comparable to those of the two-level dual-active bridge. Experimental results from a scaled test rig validate the presented concept.

Incorporating deadbeat and low‐frequency harmonic elimination in modular multilevel converters

This study shows that modular multilevel converter (MMC) can implement deadbeat control and harmonic elimination together. MMC, under single-phase deadbeat control, tracks the current reference exclusively, so that it is: (i) safe from large destructive currents of ac faults; and (ii) free from the odd harmonics generated by the non-linearities of MMC. As a deadbeat control cannot filter even harmonics on the dc-side, harmonic elimination has to be done by joint feedback–feedforward methods. However, the cost saving from capacitor size reduction, made possible by the harmonic elimination, comes to naught when large ac fault currents charge the capacitors to voltage levels destructive to insulated-gate bipolar transistors. Deadbeat, in preventing the flow of large fault currents, safeguards capacitor size reduction made possible by the harmonic elimination methods. Redundant protection by the methods enhances reliability. Claims are validated by simulations by SIMULINK of MATLAB.

A compact MMC submodule structure with reduced capacitor size using the stacked switched capacitor architecture

Modular multilevel converters (MMCs) are being developed for the grid connection of offshore wind or tidal farms. In order to reduce the construction and maintenance costs, it is desirable to reduce the weight and volume of the system. In current MMC submodule designs, the reservoir capacitor usually accounts for over 50% of the total volume and 80% of weight. This paper presents a new design concept and control principle for a submodule using the stacked switched capacitor (SSC) architecture that can significantly reduce the capacitor size in an MMC. Practical considerations for a high-voltage high-power SSC-based MMC submodule are presented in this paper, through the design of a 21-level, 40-kV (pole-pole dc), 19.1-MW, grid-connected system, and the concept is demonstrated experimenttally on a scaled-down 400-V, 12.3-Apeak laboratory prototype submodule. It is shown that with the proposed SSC architecture, the total volume of capacitors in each submodule can be reduced by more than 40% without significantly increasing the power loss.

Integration and Operation of a Single-Phase Bidirectional Inverter With Two Buck/Boost MPPTs for DC-Distribution Applications

This study is focused on integration and operation of a single-phase bidirectional inverter with two buck/boost maximum power point trackers (MPPTs) for dc-distribution applications. In a dc-distribution system, a bidirectional inverter is required to control the power flow between dc bus and ac grid, and to regulate the dc bus to a certain range of voltages. A droop regulation mechanism according to the inverter inductor current levels to reduce capacitor size, balance power flow, and accommodate load variation is proposed. Since the photovoltaic (PV) array voltage can vary from 0 to 600 V, especially with thin-film PV panels, the MPPT topology is formed with buck and boost converters to operate at the dc-bus voltage around 380 V, reducing the voltage stress of its followed inverter. Additionally, the controller can online check the input configuration of the two MPPTs, equally distribute the PV-array output current to the two MPPTs in parallel operation, and switch control laws to smooth out mode transition. A comparison between the conventional boost MPPT and the proposed buck/boost MPPT integrated with a PV inverter is also presented. Experimental results obtained from a 5-kW system have verified the discussion and feasibility.

Capacitor Ripple Current in an Interleaved PFC Converter

To achieve high-power density in power supplies, it is desirable to minimize the physical size of the energy storage capacitor. The capacitance is determined by the energy storage requirement for line outage ride-through and also the ripple current handling capability of the capacitor. Interleaving is well known as an effective method to reduce the capacitor ripple current and in cases where ripple current considerations dominate, it could reduce capacitor size. This paper presents a methodology to calculate the ripple current, both for single phase and for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</i> interleaved phases of power factor correction converters operating with constant load or a DC-DC converter load. Experimental results from a commercial power supply yielded a small error when compared to the calculations, showing that the proposed methodology has enough accuracy to be used as a design tool.

Moisture induced degradation of multilayer ceramic capacitors

When both precious metal electrode and base metal electrode (BME) capacitors were subjected to autoclave (121 °C/100% RH) testing for 500 h, it was found that the precious metal capacitors aged according to a well known aging mechanism (average capacitance degraded less than 3% from their starting values), but the BME capacitors degraded to below the −30% specification limit. One hypothesis for this new failure mechanism was that there could be oxidation or corrosion of the nickel plates. Another hypothesis was that the loss of capacitance was due to chemical changes in the barium titanate. This paper presents the evaluation of the two hypotheses and the physics of the degradation mechanism. It is concluded that there are chemical changes in the barium titanate resulting from the interaction of residual point defects from BME manufacturing and humidity in the field. The continuous reduction in capacitor size makes the newer base metal electrode capacitors more vulnerable to moisture degradation than the older generation precious metal capacitors. In addition, standard humidity life testing, such as JESD-22 THB and HAST, will likely not uncover this problem. Therefore, poor reliability due to degradation of base metal electrode multilayer ceramic capacitors may catch manufacturers and consumers by surprise.

Characteristics of 0.25 µm Ferroelectric Nonvolatile Memory with a Pb(Zr, Ti)O3 Capacitor on a Metal/Via-Stacked Plug

A 0.25-µm ferroelectric memory with 16 kbit-cell array was fabricated. A Pb(Zr, Ti)O3 (PZT) capacitor was formed on a metal(Al)/via(W)-stacked plug using low temperature metal organic chemical vapor deposition (MO-CVD). The backend process had no effect on the PZT capacitor properties. The 1×1 µm2 capacitor shows good fatigue and imprint endurance. Signal voltage on the bit-line in the cell array is 1.06 V for switching and 0.58 V for unswitching. These results agree well with the pulse-response measurement of the parallel capacitor. However, the signal voltage deviation becomes larger with the capacitor size reduction. The 16 kbit-cell array shows the column access time of 50 ns and the minimum operation voltage of 1.6 V.

Does reducing capacitance have potential for further miniaturisation of implantable defibrillators?

OBJECTIVE: To determine whether considerably smaller capacitors could replace 125 microF capacitors as the standard for use in implantable defibrillators. METHODS: Measured energy, impedance, voltage, and current delivered were compared...

Efficient Snubbers for Voltage-Source GTO Inverters

The two gate turn-off thyristors in the phase leg of a voltage-source inverter are provided with a series center-tapped inductance snubber and shunt capacitor snubbers having a single discharge resistor and only two auxiliary diodes. This arrangement minimizes the number of components and allows reduction of capacitor size, thereby reducing the snubber losses. The resistor may be replaced by a transformer which conserves a substantial part of the energy trapped in both the series and shunt snubbers.