Abstract
To achieve high-power density in power supplies, it is desirable to minimize the physical size of the energy storage capacitor. The capacitance is determined by the energy storage requirement for line outage ride-through and also the ripple current handling capability of the capacitor. Interleaving is well known as an effective method to reduce the capacitor ripple current and in cases where ripple current considerations dominate, it could reduce capacitor size. This paper presents a methodology to calculate the ripple current, both for single phase and for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</i> interleaved phases of power factor correction converters operating with constant load or a DC-DC converter load. Experimental results from a commercial power supply yielded a small error when compared to the calculations, showing that the proposed methodology has enough accuracy to be used as a design tool.
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