Reduce Design Complexity Research Articles

Design and evaluation of mobile offloading system for web-centric devices

Increasingly, smartphones are becoming one of the most popular mobile devices in the personal computing environment. As the need for a variety of mobile applications increases, the target mobile platform is a primary concern for mobile application developers. To reduce design complexity for different platforms and enhance the compatibility of applications on various mobile OSes, a JavaScript-based web environment became a main target framework for smartphone applications. Two particular characteristics of a smartphone are restricted power supply and low-end hardware resources, compared to high-end servers. Computing-intensive and rich graphics-based applications in a smartphone may fully utilize the CPU and consume a large amount of the battery power accordingly.In this paper, we propose a platform-independent mobile offloading system, which is a delegated system for a web centric devices environment. Our offloading architecture uses a built-in proxy system that splits the original JavaScript-based application codes into the following two parts: a lightweight code for the mobile client and a computationally heavy code that runs on the server system. We adopt one of the web applications utilizing a combinatory search for our case study. Our evaluation shows that our mobile offloading system reduces the response time of the application running in the web browser and enables a high workload application to run on relatively low-end mobile devices. In addition, this method reduces power consumption of the device. Therefore, this web-based offloading architecture creates a new mobile computing environment and supports various OS platforms of mobile clients.

A Sub-Microwatt Asynchronous Level-Crossing ADC for Biomedical Applications

A continuous-time level-crossing analog-to-digital converter (LC-ADC) for biomedical applications is presented. When compared to uniform-sampling (US) ADCs LC-ADCs generate fewer samples for various sparse biomedical signals. Lower power consumption and reduced design complexity with respect to conventional LC-ADCs are achieved due to: 1) replacing the n-bit digital-to-analog converter (DAC) with a 1-bit DAC; 2) splitting the level-crossing detections; and 3) fixing the comparison window. Designed and implemented in 0.18 μm CMOS technology, the proposed ADC uses a chip area of 220 × 203 μm(2). Operating from a supply voltage of 0.8 V, the ADC consumes 313-582 nW from 5 Hz to 5 kHz and achieves an ENOB up to 7.9 bits.

Reduced-Complexity Approx-Log-MAP and Max-Log-MAP Soft PSK/QAM Detection Algorithms

In this paper, we propose to reduce the complexity of both the Approx-Log-MAP algorithm as well as of the Max-Log-MAP algorithm conceived for generalized PSK/QAM detection, where only a reduced-size subset of the PSK/QAM constellation points is taken into account for producing a single soft-bit output. Although the detectors of Gray-labelled low-order PSK/QAM schemes generally produce near-horizontal EXIT curves, our proposed detectors exploit the a priori LLRs gleaned from a channel decoder in order to retain the optimum detection capability for all PSK/QAM constellations. Furthermore, we demonstrate in this paper that the widely applied MIMO schemes including V-BLAST and STBC, which invoke the proposed soft PSK/QAM detectors may also benefit from our reduced-complexity design. Our simulation results confirm that a near-capacity performance may be achieved by the proposed detectors at a substantially reduced detection complexity.

Communication controller and control unit design for Qi wireless power transfer

Abstract Qi, the wireless power standard, has been proposed to allow low power systems to receive power through wireless inductive power transfer. The standard outlines the essential, desired and optional requirements for developing the wireless power transfer platform. In this paper, we present the design and implementation results of communication controller for guided positioning single transmitter–single receiver wireless power transfer platform. Apart from the basic design, additional processing and data storage capability is introduced to make the design adaptive in terms of response time and the size of control data transfer. The method of estimating the amount of power transfer is modified to reduce design complexity and internal power consumption of power transmitter and receiver. The implementation results help to access the ratio of power transferred to resource utilization and the ratio of power transferred to power consumed in simplistic wireless power transfer platform.

Multi-variable fuzzy logic control for a class of distributed parameter systems

A multi-variable fuzzy logic controller (FLC) is proposed to control a class of distributed parameter systems (DPSs). When a DPS is transformed into finite-dimensional ordinary differential equations (ODEs) by using time/space separation, each ODE can be considered as a subsystem. According to design strategy of conventional FLC, one FLC should be designed for one subsystem. It will be very complex because there are many subsystems. In order to reduce design complexity, only a MF and a rule base are designed in the controller. For other subsystems or ODEs, their MFs can be designed equivalently by introducing scaling factors. Then, the proposed FLC has ability to control multi-variable processes. At last, the proposed FLC is applied to control a rod catalytic reaction process. The simulation results demonstrate the effectiveness of the proposed fuzzy control strategy.

Implementation of Wireless Vision Sensor Node With a Lightweight Bi-Level Video Coding

Wireless vision sensor networks (WVSNs) consist of a number of wireless vision sensor nodes (VSNs) which have limited resources i.e., energy, memory, processing, and wireless bandwidth. The processing and communication energy requirements of individual VSN have been a challenge because of limited energy availability. To meet this challenge, we have proposed and implemented a programmable and energy efficient VSN architecture which has lower energy requirements and has a reduced design complexity. In the proposed system, vision tasks are partitioned between the hardware implemented VSN and a server. The initial data dominated tasks are implemented on the VSN while the control dominated complex tasks are processed on a server. This strategy will reduce both the processing energy consumption and the design complexity. The communication energy consumption is reduced by implementing a lightweight bi-level video coding on the VSN. The energy consumption is measured on real hardware for different applications and proposed VSN is compared against published systems. The results show that, depending on the application, the energy consumption can be reduced by a factor of approximately 1.5 up to 376 as compared to VSN without the bi-level video coding. The proposed VSN offers energy efficient, generic architecture with smaller design complexity on hardware reconfigurable platform and offers easy adaptation for a number of applications as compared to published systems.

An inexpensive Arduino-based LED stimulator system for vision research

Light emitting diodes (LEDs) are being used increasingly as light sources in life sciences applications such as in vision research, fluorescence microscopy and in brain–computer interfacing. Here we present an inexpensive but effective visual stimulator based on light emitting diodes (LEDs) and open-source Arduino microcontroller prototyping platform. The main design goal of our system was to use off-the-shelf and open-source components as much as possible, and to reduce design complexity allowing use of the system to end-users without advanced electronics skills. The main core of the system is a USB-connected Arduino microcontroller platform designed initially with a specific emphasis on the ease-of-use creating interactive physical computing environments. The pulse-width modulation (PWM) signal of Arduino was used to drive LEDs allowing linear light intensity control. The visual stimulator was demonstrated in applications such as murine pupillometry, rodent models for cognitive research, and heterochromatic flicker photometry in human psychophysics. These examples illustrate some of the possible applications that can be easily implemented and that are advantageous for students, educational purposes and universities with limited resources. The LED stimulator system was developed as an open-source project. Software interface was developed using Python with simplified examples provided for Matlab and LabVIEW. Source code and hardware information are distributed under the GNU General Public Licence (GPL, version 3).

Optimizing the Number of Bits/Stage in 10-Bit, 50Ms/Sec Pipelined A/D Converter Considering Area, Speed, Power and Linearity

Pipeline ADCs are becoming popular at high speeds and with high resolution. This paper discusses the options of number of bits/stage conversion techniques in pipelined ADCs and their effect on Area, Speed, Power Dissipation and Linearity. The basic building blocks like op-amp, Sample and Hold Circuit, sub converter, DAC, Residue Amplifier used in every stage is assumed to be identical. The sub converters use flash architectures. The design is implemented using 0.18�� m CMOS technology and uses 3.3V power supply. The paper implements a 10 bit 50MSPS pipelined ADC using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion and compares them with respect to Area, Speed. Power and Linearity. The paper concludes by stating that 2bits/stage is optimum for a pipelined ADC and to reduce design complexity we can go up to 3 bits/stage. HE rapidly growing electronics has resulted in digital revolution with telephony switching systems in 1970's and continued with digital audio in 1980's and digital video in 1990's. This is expected to prevail in the present multimedia era and even can influence in future systems. Since all electrical signals in nature are analog and since most signal processing is done in the digital domain therefore, A/D and D/A converters have become a necessity. Successive approximation ADC makes single bit decision at a time while flash ADC makes all bit decisions in a single go. Successive approximation ADC is slow and occupies less area while flash ADCs are faster but area increases exponentially with bit length.

Automatic Multi-GPU Code Generation Applied to Simulation of Electrical Machines

The electrical and electronic engineerings have used parallel programming to solve their large scale complex problems for performance reasons. However, as parallel programming requires a non-trivial distribution of tasks and data, developers find it hard to implement their applications effectively. Thus, in order to reduce design complexity, we propose an approach to generate code for hybrid architectures (e.g., CPU <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$+$</tex> </formula> GPU) using OpenCL, an open standard for parallel programming of heterogeneous systems. This approach is based on Model Driven Engineering (MDE) and the MARTE profile, standard proposed by Object Management Group (OMG). The aim is to provide resources to non-specialists in parallel programming to implement their applications. Moreover, thanks to model reuse ability, we can add/change functionalities and the target architecture. Consequently, this approach helps industries to achieve their time-to-market constraints which are confirmed here by experimental tests. Besides the software development at high-level abstractions, this approach aims to improve performance by using multi-GPU environments. A case study based on the Conjugate Gradient method gives clarity to our methodology.

No-weight design of H 2 controllers for square plants

In this study, a reduced complexity design procedure for H 2 control problems of square plants is presented. First, all stabilising controllers are parameterised. Second, a modified inner-outer factorisation is defined for unstable plants and analytical formulas are developed. Third, the unique optimal controller is analytically derived by utilising the proposed parameterisation and the modified inner-outer factorisation. Finally, a simple tuning rule is developed for quantitative performance and robustness. The proposed procedure has three features: First, it is a no-weight design. The designer is not required to choose a weight. Second, this is an analytical design. The designer can directly use the developed design formulas and thus the design procedure is significantly simplified. Third, this is a quantitative design. The designer can design the controller for quantitative performance such as overshoot or stability margin. Numerical examples are given to illustrate the proposed method.

High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-level synthesis (HLS) tools have reduced design complexity but provide limited support for verification, debugging, and timing analysis. Such tools generally rely on inaccurate software simulation or lengthy register-transfer-level simulations, which are unattractive to software developers. In this paper, we introduce HLS techniques that allow application designers to efficiently synthesize commonly used ANSI-C assertions into FPGA circuits, enabling verification and debugging of circuits generated from HLS tools, while executing in the actual FPGA environment. To verify that HLS-generated circuits meet execution timing constraints, we extend the in-circuit assertion support for testing of elapsed time for arbitrary regions of code. Furthermore, we generalize timing assertions to transparently provide hang detection that back annotates hang occurrences to source code. The presented techniques enable software developers to rapidly verify, debug, and analyze timing for FPGA applications, while reducing frequency by less than 3% and increasing FPGA resource utilization by 0.7% or less for several application case studies on the Altera Stratix-II EP2S180 and Stratix-III EP3SE260 using Impulse-C. The presented techniques reduced area overhead by as much as 3x and improved assertion performance by as much as 100% compared to unoptimized in-circuit assertions.

Design of DDS based on Hybird-CORDIC Architecture

Communication technology and its signal processing are basic supportive factors of intelligent transportation system. Because of rapid progress in modern communication engineering, direct digital synthesizer (DDS) is widely used in communications system. However, traditional DDS technology is encountering challenges due to its ROM's capacity limit. The paper presents a new direct digital frequency synthesizing method based on Hybird- CORDIC (coordinated rotation digital computing) algorithm, which can calculate sin/cos value directly, improve performance, reduce size, and reduce design complexity. Accordingly, the result of field-programmable gate array (FPGA) realized with Verilog HDL language is in accord with expected requirement approvingly.

Intelligent fuzzy controller with road surfaces identifier for antilock brake system

Antilock brake system (ABS) which is a non-linear system may not be easily controlled by classical control methods. An additional challenging issue that manipulated in this search is the case of the so-called split-mu braking condition, where braking occurs while the wheels travel on different road surfaces. An intelligent fuzzy ABS controller is designed to adjust slipping performance for variety of roads. The fuzzy optimiser finds immediately the optimal wheel slips for the new surface and forces the actual wheel slips to track the optimal reference wheel slips. The simulation results show that proposed ABS algorithm ensures the avoiding of wheel’s blockage, even in different road conditions. Moreover, as a free model strategy, the obtained fuzzy control is advantageous from viewpoint of reducing design complexity and, also, anti-saturating, anti-chattering and robustness properties of the controlled system.

Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links

High-speed links which employ source synchronous clocking architectures have the ability to track correlated jitter between clock and data channels up to high frequencies. However, system timing margins are degraded by channel skew between clock and data signals and high-frequency loss. This paper describes how these key channel effects impact the jitter performance and influence the clocking architecture of high-speed source synchronous links. Tradeoffs in complexity and jitter tracking performance of common per-channel de-skew circuits are discussed, along with how band-pass filtering can be leveraged to provide additional jitter filtering at the receiver. Jitter tolerance analysis for a 10 Gb/s system shows that a near all-pass delay-locked loop (DLL) and phase-interpolator- (PI-) based de-skew performs best under low skew conditions, while, at high skew, architectures which leverage band-pass clock filtering or a phase-locked loop (PLL) for increased jitter filtering are more suitable. De-skew based on injection-locked oscillators (ILOs) offer a reduced complexity design and competitive jitter tolerance over a wide skew range.

A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling

A reconfigurable 12-b pipeline analog-to-digital converter (ADC) implemented by enabling or disabling MDAC OTAs in parallel is presented. Power scaling is achieved without varying the dc bias conditions of critical analog nodes, reducing design complexity, and allowing an existing design to be rapidly reconfigured for new specifications. The ADC can be designed for optimal power consumption over the entire sampling rate range due to the linear power scaling provided by the parallel OTA approach. The proposed ADC operates over a sampling rate range of 20 MS/s to 40 MS/s with > 62 dB SNDR. The analog power varies linearly from 36 mW at 20 MS/s to 72 mW at 40 MS/s. The ADC was fabricated in 0.18-μm CMOS process and occupies a die area of 1.9 mm2.

Concentric Permutation Source Codes

Permutation codes are a class of structured vector quantizers with a computationally-simple encoding procedure based on sorting the scalar components. Using a codebook comprising several permutation codes as subcodes preserves the simplicity of encoding while increasing the number of rate-distortion operating points, improving the convex hull of operating points, and increasing design complexity. We show that when the subcodes are designed with the same composition, optimization of the codebook reduces to a lower-dimensional vector quantizer design within a single cone. Heuristics for reducing design complexity are presented, including an optimization of the rate allocation in a shape-gain vector quantizer with gain-dependent wrapped spherical shape codebook.

CCNoC: Cache-Coherent Network on Chip for Chip Multiprocessors

As the number of cores in chip multiprocessors (CMPs) increases, cache coherence protocol has become a key issue in integration of chip multiprocessors. Supporting cache coherence protocol in large chip multiprocessors still faces three hurdles: design complexity, performance and scalability. This paper proposes Cache Coherent Network on Chip (CCNoC), a scheme that decouples cache coherency maintenance from processors and shared L2 caches and implements it completely in network on chip to free up processors and shared L2 caches from the chore of maintaining coherency, thereby reduces design complexity of CMPs. In this way, CCNoC also improves the performance of cache coherence protocol through reducing directory access latency and enhances scalability by avoiding massive directories overhead in shared L2 caches. In CCNoC, coherence state caches and active directory caches are implemented in the network interface components of network on chip to maintain cache coherence states for blocks in L1 caches and manage directory information for recently accessed blocks in L2 caches respectively. CCNoC provides a scalable CMP framework to tackle cache coherency which is the foundation of CMP. This paper evaluates the performance of CCNoC. Experimental results show that for a 16-core system, CCNoC improves performance by 3% on average over the conventional chip multiprocessor and by 10% at best, while reduces storage overhead by 1.8% and saves directory storage by 88%, showing good scalability.

Skew compensation in energy recovery clock distribution networks

In this study a new approach for skew compensation in energy recovery clock distribution networks is introduced by manipulating the operating speed of the flip-flops. The STMicroelectronics 90 nm technology allows the use of devices with different threshold voltages, namely: high threshold voltage (HVT), standard threshold voltage (SVT) and low threshold voltage (LVT). Three types of flip-flops of equal input load: fast , standard and slow are used. Timing parameters of the flip-flops are adjusted by manipulating the switching threshold of the clock port of the flip-flops. A fast/slow flip-flop has a shorter/longer T DQ delay, compared with a standard flip-flop for the same setup time (T DCLK ). Distributing flip-flops according to their delay requirements would reduce the effect of the clock's skew on the outputs of sequentially adjacent flip-flops. Owing to the slow rise time of the sinusoidal clock signal used in energy recovery clock distribution networks compared to the conventional square-wave clock, the skew that can be compensated for in energy recovery clock distribution networks using this approach would be much higher than in square-wave clock distribution networks. This approach increases the skew bounds required by algorithms to balance the skew in the clock tree leading to reduced design complexity. Theoretical analysis and simulation results using STMicroelectronics 90 nm technology at a clock frequency of 500 MHz show that this approach is feasible and effective where a skew of up to 6.2% 1of the clock period can be compensated for in the example used. In addition, constructing clock trees using the skew slack provided in the proposed technique in a new modified differed merge embedding (DME) algorithm on five benchmarks have shown that the proposed technique enables an average reduction of 11.5% in total wire length and 53.2% reduction in the number of wire elongations. Balancing the skew in the clock tree using buffers was not considered here since inserting a buffer in the clock's path eliminates the energy recovery property. As an example of illustrating the proposed methodology, the authors have used the Elmore delay model with a selected energy recovery flip-flop to verify the practicality of the proposed scheme. Better results can be obtained by using different flip-flops. The method can generally be applied to energy recovery or square-wave clocking if different flip-flops of various speeds are used.

Design and Technology Development Status and Design Considerations for Innovative Small and Medium Sized Reactors 1

There is continuing interest in Member States in the development and application of small and medium sized reactors (SMRs), i.e., the reactors with an equivalent electric power of less than 700 MW. In 2006–2007, several distinct “families” of innovative SMRs comprising more than 50 innovative concepts and designs have been analyzed or developed by national or international programs involving Argentina, Brazil, China, Croatia, France, India, Indonesia, Italy, Japan, Republic of Korea, Lithuania, Morocco, Russian Federation, South Africa, Turkey, USA, and Vietnam. Innovative SMRs are under development for all principal reactor lines. The target dates when they could be ready for deployment protrude from 2010 to 2030. The designers of innovative small and medium sized reactors pursue new design and deployment strategies making use of certain advantages provided by smaller reactor size and capacity to achieve reduced design complexity and simplified operation and maintenance requirements and to provide for incremental capacity increase through multiple plant clustering or multimodule plant construction. Competitiveness of SMRs depends on the incorporated strategies to overcome loss of economies of scale but equally it depends on finding appropriate market niches for such reactors, which generically include markets with limited investment capability potentially benefiting from reaching the targeted nuclear power station capacity incrementally, small electrical grids, off-grid locations, and nonelectrical applications of nuclear power.

Automatic boiling water reactor loading pattern design using ant colony optimization algorithm

An automatic boiling water reactor (BWR) loading pattern (LP) design methodology was developed using the rank-based ant system (RAS), which is a variant of the ant colony optimization (ACO) algorithm. To reduce design complexity, only the fuel assemblies (FAs) of one eight-core positions were determined using the RAS algorithm, and then the corresponding FAs were loaded into the other parts of the core. Heuristic information was adopted to exclude the selection of the inappropriate FAs which will reduce search space, and thus, the computation time. When the LP was determined, Haling cycle length, beginning of cycle (BOC) shutdown margin (SDM), and Haling end of cycle (EOC) maximum fraction of limit for critical power ratio (MFLCPR) were calculated using SIMULATE-3 code, which were used to evaluate the LP for updating pheromone of RAS. The developed design methodology was demonstrated using FAs of a reference cycle of the BWR6 nuclear power plant. The results show that, the designed LP can be obtained within reasonable computation time, and has a longer cycle length than that of the original design.