Reduce Design Complexity Research Articles

Single- and Three-Phase Dual-Active-Bridge DC–DC Converter Comparison for Battery Electric Vehicle Powertrain Application

Dual-active-bridge (DAB) DC–DC converters are of great interest for DC–DC conversion in battery electric vehicle (BEV) powertrain applications. There are two versions of DAB DC–DC converters: single-phase (1p) and three-phase (3p) architectures. Many studies have compared these architectures, selecting the 3p topology as the most efficient. However, there is a gap in the literature when comparing both architectures when single-phase-shift (SPS) modulation is not used to drive the converter. The aim of this study was to compare 1p and 3p DAB DC–DC converters driven by optimal modulation techniques appropriate for BEV powertrain applications. Mathematical loss models were derived for both architectures, and their performances were compared. A case study of a 100 kW converter was considered as an example to visualize the overall efficiency of the converter for each layout. The 1p DAB DC–DC converter architecture outperformed the 3p layout in both its Y–Y and D–D transformer configurations. The higher performance efficiency, lower number of components, and reduced design complexity make the 1p DAB DC–DC converter topology a favorable choice for BEV powertrain applications.

Cost and Efficiency analysis of the Secondary electric machine in a CRAFT wind turbine

Abstract Floating offshore wind turbines are ideal for deeper waters, providing access to stronger and more stable winds. The Counter-Rotating Axis Floating Tilting (CRAFT) turbine features a unique design with two counter-rotating turbines on a tilted vertical shaft and two independent electrical machines submerged below sea level. The primary generator, connected to both turbines, includes counter-rotation which doubles the relative torque, while the secondary machine controls the upper turbine. This study examines the impact of primary and secondary machine efficiency on electricity generation. The findings indicate that the primary generator’s efficiency is crucial for system stability, whereas the secondary machine’s efficiency is less critical. Reducing the secondary machine’s efficiency from 97% to 83% resulted in a 0.1% reduction in annual electricity generation. Despite the asynchronous machine’s lower efficiency, it is the economically favorable choice as the secondary machine over its synchronous counterpart due to its reduced design complexity and lower magnet costs, leading to lower overall expenses. Future research investigate how turbulent flow effects and airflow interactions between the turbines influences the model. Incorporating the cooling factor, a more comprehensive cost model and a refined dynamic stall model will also further improve the simulation’s accuracy and robustness.

Effect of swirl injection parameters on cooling performance of vortex-cooled bipropellant thruster

The cooling performance of a 10N-class gaseous Propane/GOx bi-propellant thruster with vortex cooling was investigated in this experimental study. Injecting oxidizer with a vortex was proposed as a potential cooling method for a semi-thermoplastic constructed thruster and demonstrated as a promising integrated cooling method that can be fabricated using 3D printing technology. Compared to other cooling types, vortex cooling has low system complexity and can be 3D printed as a single solid piece along with a thruster, reducing design complexity, weight, and manufacturing time. The experimental testing examined various injection configurations and their associated parameters to determine the most optimal injection combination. The test collected a comprehensive amount of data to evaluate the cooling performance with respect to varying operational parameters: oxygen-to-fuel ratio, propellant mass flow rate, and injection configuration. The study found that the acrylic chamber operated safely with a proper injection configuration identified maintaining the temperature of the thruster chamber walls below 60 °C, lower than the melting point of the acrylic material, with no damage observed. It was found that the downstream swirl injection had more favourable vortex cooling performance than the upstream injection for the scale of the thruster considered in this study.

Area and Power Optimized VLSI Architecture of Approximate Multiplier

When it comes to error-resistant applications, approximation computing offers the ability to reduce design complexity while increasing performance in terms of size, latency, and power efficiency. This brief discusses an innovative design technique for approximating multipliers. When it comes to error-resistant applications, approximation computing offers the ability to reduce design complexity while increasing performance in terms of size, latency, and power efficiency. Within the scope of this short, a unique 4-2 approximate compressor is presented. This compressor is complimentary to existing compressors that have been developed in previous work. Additionally, A proposed multiplier is built using the compressors, a constant approximation, and error correction. The simulation results show that the designed approximation multiplier performs satisfactorily. Within the Xilinx-Vivado environment, the implementation, synthesis, and simulation are carried out and recorded using the verilog HDL programming language. Key Words: approximate multiplier, exact compressor, approximate compressor and Verilog HDL.

Assembly process analysis and system design for deep in-situ fidelity corer

The deep in-situ corer is an essential tool for exploring the physical and mechanical behaviours of rocks at varying depths. Corers are multi-part products, encompassing extensive redundant assembly information stemming from the intricate assembly processes and numerous components. Thus, designing assembly systems for corers poses complexity challenges. This paper proposes an automated assembly system design framework, comprising assembly process analysis and system development. The proposed framework offers comprehensive design processes for multi-part product assembly systems, emphasizing managing information amount and complexity during the design phase. Specially, design principles and methods for minimizing information amount are analysed. And the directed graph is utilized to express the assembly information. Building upon this foundation, automated assemblability assessment and assembly process modular clustering is proposed to amalgamate and streamline assembly information, thus reducing design complexity. Leveraging pre-processed assembly information, the sub-functional solutions for assembly system are solved and optimized with AD (Axiomatic Design) and TRIZ (the Theory of Inventive Problem Solving). A case study of the deep-sea gas hydrate corer validated the effectiveness of the proposed methods in reducing information amount and yielding sub-functional solutions, thereby facilitating overall system design realization. Assembly experiments verified the designed system accomplished functional requirements. This study serves as a valuable reference for automated assembly analysis and system development for multi-part products, offering technical insights into developing deep in-situ cores from an assembly perspective.

Broadband coplanar-waveguide-based impedance-transformed Josephson parametric amplifier

Quantum-limited Josephson parametric amplifiers play a pivotal role in advancing the field of circuit quantum electrodynamics by enabling the fast and high-fidelity measurement of weak microwave signals. Therefore, it is necessary to develop robust parametric amplifiers with low noise, broad bandwidth, and reduced design complexity for microwave detection. However, current broadband parametric amplifiers either have degraded noise performance or rely on complex designs. Here, we present a device based on the broadband impedance-transformed Josephson parametric amplifier that integrates a hornlike coplanar waveguide transmission line, which significantly decreases the design and fabrication complexity while keeping comparable performance. The device shows an instantaneous bandwidth of 700 (200) MHz for 15 (20) dB gain with an average input saturation power of −110 dBm and near quantum-limited added noise. The operating frequency can be tuned over 1.4 GHz using an external flux bias. We further demonstrate the negligible backaction from our device on a transmon qubit. The amplification performance and simplicity of our device promise its wide adaptation in quantum metrology, quantum communication, and quantum information processing. Published by the American Physical Society 2024

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

Fundamental to digital signal processing applications such as the Arithmetic Logic Unit (ALU), logic gates serve as the foundational components. This paper presents NOR and NAND gates engineered for operation within the ultra-low voltage (LV) and low power domains (LP). Utilizing the floating gate MOSFET (FGMOS) approach, this study adopts a strategy to enhance performance, focusing on reducing design complexity and minimizing power consumption.The proposed FGMOS-NAND/NOR gate design is investigated for important device parameters such as power (pwr), delay (tp), power delay product (PDP), and energy delay product (EDP). At 0.7 V supply, the overall power consumption of the FGMOS NOR and NAND gates is 0.442 nW and 0.323 nW, respectively. Further, carbon nanotube field effect transistor (CNTFET) technology is used to implement NOR and NAND gates in this research work. A rigorous comparative analysis was conducted in this research study to assess the performance of non-conventional technologies, specifically field-effect transistors with floating gate (FGMOS) and carbon nanotube field-effect transistors (CNFET), in comparison to the conventional complementary metal-oxide-semiconductor (CMOS) technology. Notably, our investigation revealed that when carbon nanotube field-effect transistor (CNTFET) technology is synergistically employed in conjunction with FGMOS technology, the overall circuit performance is significantly enhanced. Furthermore, in order to estimate the robustness and reliability of the proposed designs, comprehensive analysis pertaining to delay and power-delay product (PDP) variability were meticulously carried out within the scope of this research article.

PID-Based control of sepic power stage with QS bacterial-based search algorithm for renewable energy applications

In response to the growing need for efficient power conversion in renewable energy applications, this study addresses the issue of harmonic distortion and low Power Factor (PF) values caused by non-linear loads, such as electronic devices. Low PF results in reduced efficiency, increased energy consumption, and higher costs for both consumers and utilities. Active correction, typically involving an active circuit implemented using a power converter, provides an optimal solution by offering high performance, precise regulation, and low harmonic distortion. This research proposes a Power Factor Correction (PFC) solution utilizing an Interleaved DC-DC Single Ended Primary Inductance Converter (SEPIC) for the power stage and a Proportional Integral Derivative (PID) controller for the control block, tuned by a Quorum Sensing (QS) bacterial-based search algorithm. The PID controller parameters are derived using a frequency-domain approach, which presents advantages such as reduced design complexity, improved stability margins, and enhanced SEPIC performance. Simulation results indicate reduced overshoot, settling time, rise time, and Total Harmonic Distortion (THD) percentage, as well as increased efficiency and power factor nearing unity. The proposed scheme also demonstrates improved dynamic performance for variations in load, line, and reference voltage. Owing to its high efficiency, precise voltage regulation, and minimized impact on the electrical grid, this solution is well-suited for renewable energy applications, where optimizing energy conversion and ensuring stable operation are crucial for the overall performance of renewable energy systems.

Suitability of Dual-Band, Dual-Polarized Patch Antennas with a Superstrate for the Miniaturization of Ku-Band Antenna Arrays for Automotive Applications

The extension of low-earth orbit (LEO) services to non-terrestrial mobile communications has huge potential for eliminating network white spots and providing high-speed, low-latency links with worldwide geographic coverage. State-of-the-art user terminals for mobile platforms are too large for integration into a passenger vehicle. Antenna elements loaded with a dielectric superstrate could potentially lead to a considerable miniaturization of the user terminal. As per link budget calculations, an array with a gain of 27 dBi is necessary to ensure a throughput of 25 Mbps in the downlink at the Ku-band. A conventional array with a gain of 6 dBi per element, assuming a 12 × 12 arrangement with half-wavelength spacing, would require a footprint of 36 λ2 at 10 GHz to achieve this target and appears unsuitable for automotive integration. This paper proposes a low-profile, dual-band, dual-polarized, vertically stacked patch antenna with superstrate loading and shows that the inclusion of the superstrate improves the antenna’s gain by at least 3 dB. Therefore, compared to a conventional array, a superstrate-loaded array would need only half of the number of elements to meet the target gain, thus occupying only half of the surface area, and offers better integration for automotive applications. Requiring half of the number of elements also implies considerably reduced design complexity and cost.

Research on the Diffusion Law of Fire Extinguishment Slurry to Prevent Coal Spontaneous Combustion in Regenerated Roof

ABSTRACT Coal is a major part to stable energy structure. Borehole Grouting is a primary method used for the prevention and control of coal spontaneous combustion in the regenerated roof. However, the construction design of high-position grouting for the regenerated roof lacks a sufficient theoretical foundation due to the limited advancement in theoretical research on the high-position grouting of fracture. To fill the theory research gap of high-position grouting in regenerated roof, a fracture network high-position grouting numerical model was established. Based on the numerical model and assumptions of the equivalent path, a mathematical model of fracture network high-position grouting was established and a global sensitivity analysis was conducted. The results showed that the morphology of slurry diffusion is influenced by gravity and fracture orientation. The diffusion front undergoes three successive phases of transformation: hemispherical diffusion, curved diffusion, and plane diffusion. Based on the mathematical model, the fracture aperture has the largest first-order sensitivity and total-sensitivity index to grouting pressure during the whole phase of grouting. The second-order sensitivity index between fracture aperture and slurry viscosity, grouting pipe radius, grouting rate, dip, and azimuth is greater than other parameters. By focusing on key parameters and their interactions, this research contributes to enhancing the effectiveness of grouting construction while simultaneously reducing design complexity.

Adaptive design of the magnetron injection gun using constrained multiobjective optimization

The design of the magnetron injection gun (MIG) is an inverse problem with implicit objective functions and complex constraints. The computer-aided design using an optimization algorithm is a promising method to improve the performance of the MIG and reduce design complexity and time consumption. However, the dependence on the initial structure makes it difficult to realize the real sense of using algorithms to design. To address this issue, this paper proposes an adaptive design method for the MIG. The design problem is equivalent to a constrained multiobjective optimization problem. A pseudo-random structure generation algorithm is developed based on the geometric constraints and the first-order MIG design trade-off equations. The fully parameterized MIG structure is randomly generated by the decision variables composed of the scale coefficients ranging from (0,1) and the other structural parameters. This transformation can increase the effectiveness of the randomly generated MIG structures and make it easier to set the value range of decision variables. The proposed adaptive design method is further verified by successfully designing the MIG for an 800 GHz gyrotron via the co-simulation of MATLAB and CST.

A Survey of the Different Intelligent Algorithms for the VLSI-Based Design Flows for Various Embedded Applications in Electronics Engineering

The AI/ML applications and techniques that could be applied in VLSI design technology are briefly reviewed in this study. The integrated circuit (IC) industry will undoubtedly face challenges in the nano-meter regime related to the research and development of methods that could reduce design complexity brought on by increasing process variability and reducing the turnaround time of chip manufacture. The majority of the traditional methods utilized for these tasks involve manual labor, which requires time and resources. Contrarily, the unique learning strategies of artificial intelligence enable the design and testing of very large-scale integration (VLSI) to benefit from several innovative automated ways (AI). Artificial intelligence (AI) and machine learning (ML) algorithms use automated learning algorithms to reduce the time and effort needed to interpret and process data within and across different abstraction levels, enhancing IC yield and accelerating manufacturing turnaround. This article examines the formerly employed automated AI/ML methods for VLSI design and manufacture. The project that is the subject of this paper is a P.G. (M.Tech) student's technical seminar report, which is a component of the seminar that each student must deliver on any topic during the second semester of the PG program.

Blueprint for a High-Performance Fluxonium Quantum Processor

The technological development of hardware heading toward universal fault-tolerant quantum computation requires a large-scale processing unit with high performance. While fluxonium qubits are promising with high coherence and large anharmonicity, their scalability has not been systematically explored. In this work, we propose a superconducting quantum information processor based on compact high-coherence fluxoniums with suppressed crosstalk, reduced design complexity, improved operational efficiency, high-fidelity gates, and resistance to parameter fluctuations. In this architecture, the qubits are readout dispersively using individual resonators connected to a common bus and manipulated via combined on-chip RF and DC control lines, both of which can be designed to have low crosstalk. A multi-path coupling approach enables exchange interactions between the high-coherence computational states and at the same time suppresses the spurious static ZZ rate, leading to fast and high-fidelity entangling gates. We numerically investigate the cross resonance controlled-NOT and the differential AC-Stark controlled-Z operations, revealing low gate error for qubit-qubit detuning bandwidth of up to 1 GHz. Our study on frequency crowding indicates high fabrication yield for quantum processors consisting of over thousands of qubits. In addition, we estimate low resource overhead to suppress logical error rate using the XZZX surface code. These results promise a scalable quantum architecture with high performance for the pursuit of universal quantum computation.

Simultaneous reduced‐order control and fault detection for discrete‐time switched systems with relaxed persistent dwell time regularity

AbstractThis paper focuses on the problem of simultaneous control and fault detection (FD) for discrete‐time switched systems. The main goal is to develop a control/detection unit (CDU) associated with a switching law to control the system and detect faults simultaneously. When the switched systems are with partial measurable states, we directly use these states to construct partial control and FD signals. Next, the reduced‐order CDU is designed to generate the other control and FD signals. Compared with existing results based on full‐order CDU, the proposed results lead to less conservatism and reduce design complexity. The switching law is constructed in the frame of persistent dwell time (PDT) switching. A novel switching number constraint condition is introduced, which further relaxes the restrictions on the dwell time of switching processes of PDT. The less restriction on dwell time degrades the performance requirement of each subsystem and upgrades the degree of freedom for switching law design. Based on the proposed results, a class of nonweighted performance indexes is introduced to characterize the fault sensitivity and robustness. Finally, the effectiveness of the proposed method is illustrated by an example.

Analyzing Security Vulnerabilities Induced by High-level Synthesis

High-level synthesis (HLS) is essential to map the high-level language (HLL) description (e.g., in C/C++) of hardware design to the corresponding Register Transfer Level (RTL) to produce hardware-independent design specifications with reduced design complexity for ASICs and FPGAs. Adopting HLS is crucial for industrial and government applications to lower development costs, verification efforts, and time-to-market. Current research practices focus on optimizing HLS for performance, power, and area constraints. However, the literature does not include an analysis of the security implications carried through HLS-generated RTL translations (e.g., from an untimed high-level sequential specification to a fully scheduled implementation). This article demonstrates the evidence of security vulnerabilities that emerge during the HLS translation of a high-level description of system-on-chip (SoC) intellectual properties to their corresponding RTL. The evidence provided in this manuscript highlights the need for (a) guidelines for high-level programmers to prevent these security issues at the design time and (b) automated HLS verification solutions that cover security in their optimization flow.

Using the REA Data Model in Order to Reduce Design Complexity in an Inventory Management Relational Database, and the Need for a Relational Database Complexity Metric.

With the extensive use of relational databases in the business environment there is a need to reduce database complexity in order to avoid data inconsistency and redundancy, which can provide a company with unreliable and/or meaningless data and information.
 The use of the REA Data Model in database design can significantly help with this problem. The model can eliminate the need for unnecessary data artifacts which should only be generated by the system when needed.
 This paper also addresses the need for a Relational Database Complexity Metric. A simple and easy to understand metric is presented.

Area and energy efficient shift and accumulator unit for object detection in IoT applications

Convolutional Neural Networks (CNNs) exhibit significant performance enhancements in several machine learning tasks such as surveillance, intelligent transportation, smart grids and healthcare systems. With the proliferation of physical things being connected to internet and enabled with sensory capabilities to form an Internet of Thing (IoT) network, it is increasingly important to run CNN inference, a computationally intensive application, on the resource constrained IoT devices. Object detection is a fundamental computer vision problem that provides information for image understanding in several artificial intelligence (AI) applications in smart cities. Among various object detection algorithms, CNN has emerged as a new paradigm to improve the overall performance. The Multiply-accumulate (MAC) operations, which are used repeatedly in the convolution layers of CNN, hold extreme computational complexity. Hence, the overall computational workloads and their respective energy consumption of any CNN applications are on the rise. To overcome these escalating challenges, approximate computing mechanism has played a vital role in reducing power and area of computation intensive CNN applications. In this paper, we have designed an approximate MAC architecture, termed Shift and Accumulator Unit (SAC), for the error-resilient CNN based object detection algorithm targeting embedded platforms. The proposed computing unit deliberately trades accuracy to reduce design complexity and power consumption, thus suiting the resource constrained IoT devices. The pipeline architecture of the SAC unit saves approximately 1.8× clock cycles than the non-pipeline SAC architecture. The performance evaluation shows that the proposed computing unit has better energy efficiency and resource utilization than the accurate multiplier and state-of-the-art approximate multipliers without noticeable deterioration in overall performance.

Thermodynamic mathematical modelling and analysis of vapour absorption refrigeration system using a novel ant lion optimiser

In an advanced industrial effort, the role of vapour absorption refrigeration system plays a major role. However, the significant eco-friendly and the required cooling capacity rate are the major challenges in the design of refrigeration systems for industrial applications. For this reason, the novel ant lion optimiser (AO) based thermodynamic modelling and analysis of single-effect vapour absorption refrigeration model is proposed in this research for industrial buildings. Here, Lithium Bromide and water (LiBr-H2O) are taken as an absorbent in the refrigeration system. Therefore, an effective novel 5 kW cooling capacity of LiBr-H2O depending upon the vapour absorption refrigeration structure is designed. The analysis of this research is done by the improved polynomial curve fit equation. Moreover, the coefficient of performance of the absorption cycle is optimised using a novel AO method. The implementation of this work is done on the MATLAB platform. In addition, the developed novel 5 kW cooling capacity with AO is applied in industrial building applications to validate the successive measure of the projected replica. Furthermore, the outcome of the projected design is compared with different existing refrigeration designs and the best results by reducing design complexity.

Design of iRLS Algorithm With/Without Pre-Filter for Antenna Beam Forming Technique

Beamforming is one of the most significant processes in smart antennas. To change the antenna beam pattern is the major function of beamforming for a given angle. The algorithm that is adaptive beamforming is utilized to choose the conventional weights of each array element from acquired data of array antenna to extract the desired source signal while cancelling noise and interference. A lot of algorithms are already existing for antenna beamforming technique but they all experience low convergence. So this paper deals with an iRLS algorithm for antenna beamforming technique with Particle Swarm Optimized (PSO) FFT filter. As a result, antenna beamforming based on iRLS shows fast convergence with reduced design complexity. The overall work is simulated in MATLAB. The parameters like amplitude, bit error rate, capacity, SINR and error function values are evaluated. Our work is compared with existing Applebaum, Recursive Least Squares (RLS) (with/without filter) and Least Mean Square (LMS) algorithm. Fast convergence is occurred by iRLS when compared with existing algorithms. The iRLS is converged at 90th iteration, whereas existing algorithms likewise RLS with pre-filter, RLS without pre-filter, LMS and Applebaum is converged at 200, 400, 600 and 850th iteration. So here, our proposed iRLS gives better performance when compared with others.

Design and simulation of DC regulated circuit for current source input type based on Tina-TI

In the multi-output high-voltage isolated power supply for solid-state switches, LCL resonant network is used to obtain the constant current source on the bus, and the bus current is independent of the load. Therefore, the secondary side of the toroidal transformer needs to use the current input voltage regulator circuit. When the input is a current source instead of a voltage source, the traditional voltage regulator circuit is no longer applicable. Therefore, this paper focuses on the study of dc voltage regulated circuit with current source input. Compared with the traditional linear regulated power supply, switching power supply has the advantages of high efficiency, large output power, small size, light weight and low cost. In this paper, pulse width modulation (PWM) technology is used to control the switching on and off, and UC3843 is used to design a switch type regulated power supply with small size, simple circuit, adjustable output and over voltage protection function. Tina-TI software was used for simulation analysis, and the main circuit and control circuit were built. The current source of 1.25A and 40kHz output by the secondary side of the toroidal transformer is converted into a stable 10V DC voltage source, which verified the correctness of the design. Tina-TI software can be used to analyze and design power supply with different requirements, improve power efficiency, reduce design complexity, and thus shorten development cycles.