Redox Transistor Research Articles

Magnetization Vector Rotation Reservoir Computing Operated by Redox Mechanism.

Physical reservoir computing is a promising way to develop efficient artificial intelligence using physical devices exhibiting nonlinear dynamics. Although magnetic materials have advantages in miniaturization, the need for a magnetic field and large electric current results in high electric power consumption and a complex device structure. To resolve these issues, we propose a redox-based physical reservoir utilizing the planar Hall effect and anisotropic magnetoresistance, which are phenomena described by different nonlinear functions of the magnetization vector that do not need a magnetic field to be applied. The expressive power of this reservoir based on a compact all-solid-state redox transistor is higher than the previous physical reservoir. The normalized mean square error of the reservoir on a second-order nonlinear equation task was 1.69 × 10-3, which is lower than that of a memristor array (3.13 × 10-3) even though the number of reservoir nodes was fewer than half that of the memristor array.

Enhanced synaptic characteristics of H x WO3-based neuromorphic devices, achieved by current pulse control, for artificial neural networks

Artificial synapses capable of mimicking the fundamental functionalities of biological synapses are critical to the building of efficient neuromorphic systems. We have developed a H x WO3-based artificial synapse that replicates such synaptic functionalities via an all-solid-state redox transistor mechanism. The subject synaptic-H x WO3 transistor, which operates by current pulse control, exhibits excellent synaptic properties including good linearity, low update variation and conductance modulation characteristics. We investigated the performance of the device under various operating conditions, and the impact of the characteristics of the device on artificial neural network computing. Although the subject synaptic-H x WO3 transistor showed an insufficient recognition accuracy of 66% for a handwritten digit recognition task with voltage pulse control, it achieved an excellent accuracy of 88% with current pulse control, which is approaching the 93% accuracy of an ideal synaptic device. This result suggests that the performance of any redox-transistor-type artificial synapse can be dramatically improved by current pulse control, which in turn paves the way for further exploration and the evolution of advanced neuromorphic systems, with the potential to revolutionize the artificial intelligence domain. It further marks a significant stride towards the realization of high-performance, low-power consumption computing devices.

Tunable electrical field-induced metal-insulator phase separation in LiCoO2 synaptic transistor operating in post-percolation region

While mixed ionic-electronic conductors with metal-insulator transition (MIT) are promising candidates for designing neuromorphic computing hardware, the fundamentals of resistive switching in these materials are yet to be well understood. This work studies the switching mechanism of the three-terminal nonvolatile redox transistor (NVRT) containing the LiCoO2 (LCO) channel layer with tunable preferred crystallographic orientation. We used atomic force microscope nanotomography to reconstruct the 3D conductance map of NVRTs, that reveals the applied gate electric-field induces the MIT via reversible phase separation in the LCO channel layer, with the nonequilibrium thermodynamics analytical model providing validation to this mechanism. By operating in the post-percolation region, the memory properties can continuously adjust the conductance states of NVRTs. The percolation conductance mechanism via the metallic LCO phase ensures the exceptional linearity and reproducibility of conductance modulation, whereas the field-, rather than current-, induced transition results in the low energy consumption replicating key features of the living neural cells.

Selective separation of monovalent anions by PPy/pTS membrane electrodes in redox transistor electrodialysis

Selective separation of nitrate over chloride is crucial for eutrophication mitigation and nitrogen resource recovery but remains a challenge due to their similar ionic radius and the same valence. Herein, a polypyrrole membrane electrode (PME) was fabricated by polymerization of pyrrole (Py) and p-toluenesulfonate (pTS), which was used as a working electrode in redox transistor electrodialysis. The anions in the source solution were first incorporated into the PME at reduction potentials and then released to receiving solution at oxidation potentials. Pulse widths and potentials were optimized to maximize the ion separation performance of PME, resulting in the improvement of NO3−/Cl− separation factor up to 6.93. The ion distributions in various depths of PME indicated that both NO3− and Cl− were incorporated into PME at negative potentials. Then, NO3− was preferentially released from PME at positive potentials, but most Cl− was retained. This was ascribed to the high binding energy between Cl− and PPy/pTS structure, which was 51.4% higher than that between NO3− and PPy/pTS structure. Therefore, the higher transport rate of NO3− in comparison with Cl− was achieved, leading to a high NO3− selectivity over Cl−. This work provides a promising avenue for the selective separation of nitrate over chloride, which may contribute to nitrogen resource recycling and reuse.

Understanding synaptic characteristics of nonvolatile analog redox transistor based on mobile ion-modulated-electrolyte thickness model for neuromorphic applications

Linear and symmetric updates of the channel current of the redox transistor are involved in bulk mobile ion motion. In this study, we introduce the concept of a variable effective electrolyte thickness (teff) precisely tuned by gate voltage-driven ions into the drain current equation of a conventional transistor. In order to understand the switching characteristics of a nonvolatile analog redox transistor that serves as an artificial synapse for neuromorphic systems, we developed a physics-based model in MATLAB. The simulated synaptic update curves obtained using identical gate pulses were in good agreement with the fabricated Cu-ion-actuated CuOx/HfOx/WOx redox transistor. We then analyzed the impact of geometrical and material-related parameters on the synaptic behavior, taking into account the ion speed and the degree of allowable electric field through the electrolyte. In addition, we performed Monte Carlo simulation to create a non-uniformly changed teff circumstance. With this, we reproduced the fluctuated update of the channel current every gate pulse, which is occasionally observed experimentally when mobile ions are easily moved randomly. Our simulation results revealed that the redox transistor immune to the unevenly changed teff can be achieved by lowering the ion velocity.

Transmembrane transport characterization across ionic redox transistors using surface-tracked scanning ion conductance microscopy

A fundamental understanding of ion transport at the nanoscale is critical to the development of efficient chemical separation membranes, catalysts, ionic/bio-inspired materials, and its scale up into multi-functional ionic devices. Electrochemical imaging using scanning probe microscopy hardware has provided a method to visualize and understand processes that occur at the surface of ionic active materials. The suite of scanning probe microscopy techniques developed over the last few years are limited to imaging surface-level phenomena and have not been applied to investigate transmembrane properties of synthetic and natural membranes with high spatial and temporal resolution. In this article, we demonstrate the application our recently developed ‘surface-tracked scanning ion conductance microscopy’ technique to characterize voltage-regulated ion transport in an ionic redox transistor. The ionic redox transistor exhibits controlled transmembrane ion transport as a function of its electrochemical redox state. The technique presented in this article uses shear force measured between the nanopipette and ionic substrate to image topography of the porous substrate and simultaneously characterize topography-correlated transmembrane transport through the ionic redox transistor. The transmembrane conductance measured across an array of pores within the ionic redox transistor varies from 0.004 μS/cm (OFF state) to 0.015 μS/cm (ON state). We anticipate that the spatial correlation of transmembrane ion transport in the ionic redox transistor would result in a scale up into smart membrane separators for energy storage, neuromorphic circuits, and desalination membranes.

Ultrahigh‐Speed In‐Memory Electronics Enabled by Proximity‐Oxidation‐Evolved Metal Oxide Redox Transistors (Adv. Mater. 20/2022)

In-Memory Processing To achieve in-memory processing, the development of an ultrafast and reconfigurable multi-terminal device is required. In article number 2200122, Mohit Kumar, Hyungtak Seo, and co-workers develop a proof-of-concept ultrafast (≈42 ns) and programmable redox thin-film transistor, which is successfully utilized to build in-memory electronics, including logic-in-memory processing, on-demand multiterminal addressable memory, learning, pattern recognition, and classification.

Ultrahigh-Speed In-Memory Electronics Enabled by Proximity-Oxidation-Evolved Metal Oxide Redox Transistors.

The pursuit of a universal device that combines nonvolatile multilevel storage, ultrafast writing/erasing speed, nondestructive readout, and embedded processing with low power consumption demands the development of innovative architectures. Although thin-film transistors and redox-based resistive-switching devices have independently been proven to be ideal building blocks for data processing and storage, it is still difficult to achieve both well-controlled multilevel memory and high-precision ultrafast processing in a single unit, even though this is essential for the large-scale hardware implementation of in-memory computing. In this work, an ultrafast (≈42ns) and programable redox thin-film transistor (ReTFT) memory made of a proximity-oxidation-grown TiO2 layer is developed, which has on/off ratio of 105 , nonvolatile multilevel analog storage with a long retention time, strong durability, and high reliability. Utilizing the proof-of-concept ReTFTs, circuits capable of performing fundamental NOT, AND, and OR operations with reconfigurable logic-in-memory processing are developed. Further, on-demand signal memory-processing operations, like multi-terminal addressable memory, learning, pattern recognition, and classification, are explored for prospective application in neuromorphic hardware. This device, which operates on a fundamentally different mechanism, presents an alternate solution to the problems associated with the creation of high-performing in-memory processing technology.

Solid-State Electrochemical Random Access Memory for in-Memory Computing

Novel approaches to computing are needed to accommodate the rapid increases in data processing needs. Standard von Neumann architectures may not be optimal for operations like machine learning due to the high energy costs of moving data between separate processor and memory elements. In-memory computing with combined logic and memory functionality is a promising energy-efficient solution. Filament-based phase-change memory and resistive random access memory are well-investigated approaches to in-memory computing; however, they suffer from unreliable switching due to the stochastic motion of ions within the filament. This results from the positive feedback process associated with filament-based memories.In this work, we develop electrochemical random-access memory (ECRAM) that uses the 3D concentration of oxygen vacancy ions to store information1,2. We sandwich an ion-conducting, electron-blocking solid electrolyte between the reservoir and switching layers, both mixed ionic and electronic conductors (MIECs). Due to essential zero electronic conductivity, the ion conductor blocks the nonuniform joule heating positive feedback that results in filament formation. Instead, oxygen vacancies are uniformly distributed in the 3D bulk. This electrochemical memory cell is therefore sensitive to the average statistical behavior of all ions, as opposed to the stochastic behavior of a small number of ions in the filament. This average ion concentration yields the analogue information state.We show that small, short electrochemical voltage pulses (+/-1.5V, 2 μs) can be used to shuttle vacancies between the MIECs; this enables reliable, linear, and deterministic switching behavior with hundreds of information states. At the same time, the materials are CMOS compatible with long endurance and information retention. The switching and retention times are dependent upon the ability of the materials to allow reversible changes in the oxygen stoichiometry, analogous to an “oxygen battery,” as well as the ionic resistance of the electrolyte. These ECRAM cells not only solve the longstanding problems within resistive memory, but also present significant opportunities for future research onto different nonstoichiometric transition metal oxides.Reference:1 Y. Li et al. “Filament-free bulk resistive memory enables deterministic analogue switching,” Adv Mater, 32, 202003984 (2020)2. Y. Li et al. "Low-Voltage, CMOS-Free Synaptic Memory Based on LiXTiO2 Redox Transistors," ACS Appl. Mater. Interfaces, 11, 42, 38982–38992 (2019) Figure 1

In situ Parallel Training of Analog Neural Network Using Electrochemical Random-Access Memory.

In-memory computing based on non-volatile resistive memory can significantly improve the energy efficiency of artificial neural networks. However, accurate in situ training has been challenging due to the nonlinear and stochastic switching of the resistive memory elements. One promising analog memory is the electrochemical random-access memory (ECRAM), also known as the redox transistor. Its low write currents and linear switching properties across hundreds of analog states enable accurate and massively parallel updates of a full crossbar array, which yield rapid and energy-efficient training. While simulations predict that ECRAM based neural networks achieve high training accuracy at significantly higher energy efficiency than digital implementations, these predictions have not been experimentally achieved. In this work, we train a 3 × 3 array of ECRAM devices that learns to discriminate several elementary logic gates (AND, OR, NAND). We record the evolution of the network’s synaptic weights during parallel in situ (on-line) training, with outer product updates. Due to linear and reproducible device switching characteristics, our crossbar simulations not only accurately simulate the epochs to convergence, but also quantitatively capture the evolution of weights in individual devices. The implementation of the first in situ parallel training together with strong agreement with simulation results provides a significant advance toward developing ECRAM into larger crossbar arrays for artificial neural network accelerators, which could enable orders of magnitude improvements in energy efficiency of deep neural networks.

(Keynote) Proton-Tunable Analog Transistor Using a Coordination Polymer

Artificial neural networks (ANN), an alternative to digital logic, can supersede Moore’s law limitations, solve complex non-numeric problems, and are compatible with low-power analog hardware that can reduce energy consumption. Analog devices emulating nerve synapses offer an alternative to digital logic for ANN. Ion-based switches, such as memristors, could potentially address these challenges. However, correlated ion and charge transport in their conducting channels and numerous issues with the switching materials are a barrier to development and optimization of these potentially revolutionary concepts. Recently, Talin and coworkers developed a novel three-terminal redox transistor (RT)[1] based on conducting organic polymers (PEDOT:PSS) that can overcome the inherent limitations of two-terminal memristors for ANN and low-power computing (Fig. 1). Dozens to hundreds of conducting states are feasible, with fast switching and much lower switching voltages than CMOS transistors. They also demonstrated that these polymer redox transistors endure >109 ‘read-write’ operations and project that switching times <100 ns are feasible.[2] Gaining fundamental insight into the performance-controlling phenomena in ion-based switches such as the RT is difficult because ionic and electronic charge transport are correlated in these devices. In the RT, the complex morphology of the polymer electrodes, which have both ordered and disordered regions resembling “cooked spaghetti”[3] affects the density of states (DOS), leading to carrier concentration-dependent mobilities.[4] Consequently, disentangling the correlated effects of morphology, composition, and device architecture requires new synthetic approaches, much greater control over disorder, and operando experimental probes that can generate spatially resolved potentials and composition and microstructural maps.We are developing self-assembled nanoporous materials (SNM) as a new class of mixed conductors to enable independent control of ion and electronic charge transport. SNM offer unprecedented control over porosity to confine and rapidly transport ions, as well as long-range order and synthetic versatility to tailor electronic conductivity. In this presentation we will discuss the requirements for such materials, in particular, highlighting the potential of nanoporous framework materials to provide tailorable pore dimensions with chemical functionalities and redox behavior suitable for ion-based switching. As a starting point for determining structure-function relationships, we are considering redox-active MOFs, which can provide tunable electrical conductivity and fast ion transport combined with a structure having long-range order. An experimental device incorporating these materials will be described to illustrate the potential for using MOFs in RT devices. Fabrication methods and device assembly will also be discussed. Data from operando measurements of local composition and state-of-charge will be presented together with maps relating local morphology with conductivity to create a detailed picture of material and device performance. Finally, results from analytical modeling will be compared with these experimental to determine the validity of current models to describe the coupled ion and charge transport. Y. van de Burgt; E. Lubberman; E. J. Fuller; S. T. Keene; G. C. Faria; S. Agarwal; M. J. Marinella; A. A. Talin; A. Salleo "A non-volatile organic electrochemical device as a low-voltage artificial synapse for neuromorphic computing," Nat. Mater. 2017, 16, 414, 10.1038/nmat4856.E. J. Fuller; S. T. Keene; A. Melianas; Z. Wang; S. Agarwal; Y. Li; Y. Tuchman; C. D. James; M. J. Marinella; J. J. Yang; A. Salleo; A. A. Talin "Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing," Science 2019, 364, 570, 10.1126/science.aaw5581.R. Noriega; J. Rivnay; K. Vandewal; F. P. V. Koch; N. Stingelin; P. Smith; M. F. Toney; A. Salleo "A general relationship between disorder, aggregation and charge transport in conjugated polymers," Nat. Mater. 2013, 12, 1038, 10.1038/nmat3722.J. T. Friedlein; J. Rivnay; D. H. Dunlap; I. McCulloch; S. E. Shaheen; R. R. McLeod; G. G. Malliaras "Influence of disorder on transfer characteristics of organic electrochemical transistors," Appl. Phys. Lett. 2017, 111, 10.1063/1.4993776. Figure 1

(Invited) Ion Tunable Electronic Materials Systems for Neuromorphic Computing

Tuning electronic conductance through solid state electrochemical ion insertion has emerged as a promising technology to enable next-generation, ultralow energy computing architectures1-3. Unlike two-terminal non-volatile memory elements, the three-terminal redox transistor decouples the ‘write’ and ‘read’ operations using a ‘gate’ electrode to tune the conductance state through charge transfer reactions involving ion injection into the channel electrode through a solid-state electrolyte. The insertion of ions into the bulk of the channel acts to dope the material through a gradual composition modulation that leads up to thousands of finely spaced conductance levels (synaptic weights) with near-ideal analog behavior. These properties enable low-energy operation without compromising analog performance and non-volatility. However, the strong coupling of ionic and electronic processes sharply challenges our current understanding of solid-state electrochemical systems, particularly at decreasing dimensions and timescales relevant to computing technology. In my talk I will discuss the rich portfolio of challenging, exciting fundamental science questions about ion tunable electronic materials systems and how we can harness these to realize a new paradigm for low power neuromorphic computing. Fuller, E. J.; El Gabaly, F.; Leonard, F.; Agarwal, S.; Plimpton, S. J.; Jacobs-Gedrim, R. B.; James, C. D.; Marinella, M. J.; Talin, A. A., Li-Ion Synaptic Transistor for Low Power Analog Computing. Advanced Materials 2017, 29.Fuller, E. J.; Keene, S. T.; Melianas, A.; Wang, Z. R.; Agarwal, S.; Li, Y. Y.; Tuchman, Y.; James, C. D.; Marinella, M. J.; Yang, J. J.; Salleo, A.; Talin, A. A., Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing. Science 2019, 364 (6440), 570.Li, Y. Y.; Fuller, E. J.; Asapu, S.; Agarwal, S.; Kurita, T.; Yang, J. J.; Talin, A. A., Low-Voltage, CMOS-Free Synaptic Memory Based on LixTiO2 Redox Transistors. Acs Applied Materials & Interfaces 2019, 11 , 38982.

Surface-Dependent Performance of Ultrathin TiN Films as an Electrically Conducting Li Diffusion Barrier for Li-Ion-Based Devices.

An in-depth understanding of lithium (Li) diffusion barriers is a crucial factor for enabling Li-ion-based devices such as three-dimensional (3D) thin-film batteries and synaptic redox transistors integrated on silicon substrates. Diffusion of Li ions into silicon can damage the surrounding components, detach the device itself, lead to battery capacity loss, and cause an uncontrolled change of the transistor channel conductance. In this study, we analyze for the first time ultrathin 10 nm titanium nitride (TiN) films as a bifunctional Li-ion diffusion barrier and current collector. Thermal atomic layer deposition (ALD) and pulsed chemical vapor deposition (pCVD) are employed for manufacturing ultrathin films. The 10 nm ALD films demonstrate excellent blocking capability with an insertion of only 0.03 Li per TiN formula unit exceeding 200 galvanostatic cycles at 3 μA/cm2 between 0.05 and 3 V versus Li/Li+. An ultralow electrical resistivity of 115 μΩ cm is obtained. In contrast, a partial barrier breakdown is observed for 10 nm pCVD films. High surface quality with low contamination is identified as a key factor for the excellent performance of ALD TiN. Conformal deposition of 10 nm ALD TiN in 3D structures with high aspect ratios of up to 20:1 is demonstrated. The measured capacities of the surface area-enhanced samples are in good agreement with the expected values. High-temperature blocking capability is proven for a typical electrode crystallization step. Ultrathin ALD TiN is an ideal candidate for an electrically conducting Li-ion diffusion barrier for Si-integrated devices.

Potassium-Ion Recovery with a Polypyrrole Membrane Electrode in Novel Redox Transistor Electrodialysis.

Conductive polymers are potential selective ion-exchange membrane materials. In this study, a novel redox transistor electrodialyzer consisting of two chambers separated by a polypyrrole (PPy) membrane electrode was designed for potassium ion (K+) recovery from water. The PPy membrane electrode was fabricated by depositing PPy on a stainless-steel wire mesh through the electrochemical method. Based on ion-exchange results, the PPy membrane exhibited electrodialysis selectivity for K+ in the presence of Na+, with a K+/Na+ separation factor of 2.10. Adding modified active carbon to PPy provided a larger electroactive area and better conductivity, resulting in higher ion-exchange capacity (1.04 mmol/L) compared with the original PPy membrane. Even for seawater containing a very low concentration of K+ (16.18 mmol/L), the PPy membrane still demonstrated K+ selectivity (separation factor of 2.18). Energy consumption in the electrodialyzer was 3.80 kW h/kg K, which was 37% lower than that in traditional electrodialysis. Furthermore, the PPy membrane exhibited antiscaling/fouling ability with the help of a pulse voltage. These findings highlight a novel redox transistor electrodialysis process with great potential application in K+ recovery from wastewater with relatively low energy consumption.

Redox transistors for neuromorphic computing

Efficiency bottlenecks inherent to conventional computing in executing neural algorithms have spurred the development of novel devices capable of “in-memory” computing. Commonly known as “memristors,” a variety of device concepts including conducting bridge, vacancy filament, phase change, and other types have been proposed as promising elements in artificial neural networks for executing inference and learning algorithms. In this article, we review the recent advances in memristor technology for neuromorphic computing and discuss strategies for addressing the most significant performance challenges, including nonlinearity, high read/write currents, and endurance. As an alternative to two-terminal memristors, we introduce the three-terminal electrochemical memory based on the redox transistor (RT), which uses a gate to tune the redox state of the channel. Decoupling the “read” and “write” operations using a third terminal and storage of information as a charge-compensated redox reaction in the bulk of the transistor enables high-density information storage. These properties enable low-energy operation without compromising analog performance and nonvolatility. We discuss the RT operating mechanisms using organic and inorganic materials, approaches for array integration, and prospects for achieving the device density and switching speeds necessary to make electrochemical memory competitive with established digital technology.

Low-Voltage, CMOS-Free Synaptic Memory Based on LiXTiO2 Redox Transistors.

Neuromorphic computers based on analogue neural networks aim to substantially lower computing power by reducing the need to shuttle data between memory and logic units. Artificial synapses containing nonvolatile analogue conductance states enable direct computation using memory elements; however, most nonvolatile analogue memories require high write voltages and large current densities and are accompanied by nonlinear and unpredictable weight updates. Here, we develop an inorganic redox transistor based on electrochemical lithium-ion insertion into LiXTiO2 that displays linear weight updates at both low current densities and low write voltages. The write voltage, as low as 200 mV at room temperature, is achieved by minimizing the open-circuit voltage and using a low-voltage diffusive memristor selector. We further show that the LiXTiO2 redox transistor can achieve an extremely sharp transistor subthreshold slope of just 40 mV/decade when operating in an electrochemically driven phase transformation regime.

Parallel Programming of an Ionic Floating-Gate Memory Array for Scalable Neuromorphic Computing

Neuromorphic computers could overcome efficiency bottlenecks inherent to conventional computing through parallel programming and read out of artificial neural network weights in a crossbar memory array. However, selective and linear weight updates and <10nA read currents are required for learning that surpasses conventional computing efficiency. We introduce an ionic floating-gate memory array [1] based upon a polymer redox transistor connected to a volatile conductive-bridge memory (CBM). Selective and linear programming of a transistor array is executed in parallel by overcoming the bridging threshold of the CBMs. Synaptic weight readout with currents <10nA is achieved by diluting the conductive polymer in an insulating channel to decrease the conductance. The redox transistors endure > 109 ‘read-write’ operations and support > 1MHz ‘read-write’ frequencies. [1] Fuller et. al. Science, 2019 (in press)

Low-Voltage, CMOS-Free Synaptic Memory Based on LiXTiO2 Redox Transistors

Neuromorphic computers based on analog neural networks aim to substantially lower computing power by reducing the need to shuttle information between memory and logic units. Artificial synapses containing analog, non-volatile conductance states enable direct computation using memory elements; however, most non-volatile analog memories require high voltages and current densities, and have nonlinear and unpredictable weight updates. Here, we develop a redox transistor based on electrochemical ion insertion into LixTiO2 that not only enables linear weight updates at low current densities, but also has no baseline open-circuit voltage. The absence of an open-circuit voltage offset enables its pairing with a diffusive memristor acting as selector to create a Si-free synaptic memory cell with write voltages as low as 170 mV. We further show that the LixTiO2 redox transistor can achieve an extremely sharp transistor subthreshold slope of just 40 mV/decade (at 80° C) when operating in an electrochemically driven phase transformation regime.

(Invited) Energy Efficient Neural Network Training with Analog Synapses: Challenges and Opportunities

As the exponential performance-per-watt gains from traditional CMOS scaling end, new computing paradigms are being seriously considered. Neural network algorithms such as deep neural networks (DNN) offer compatibility with analog, in-memory computing paradigm with the potential for orders of magnitude improvement over today’s special purpose chips. In this analog paradigm, neural network weights are stored as conductance levels in a physical matrix of tunable nonvolatile resistance memory devices, such as oxide-based resistive memory (ReRAM), phase change memory (PCRAM), three terminal floating gate, and redox memories. Our detailed analysis of a neural processing unit (NPU) core analog block based on these devices can perform individual inference and training operations at energies as low as 10 fJ per operation (100 TOPs/W), achieving greater than a 100x improvement over the best modern digital neural training processors. This will achieve revolutionary performance for modern deep neural network accelerators, which are currently found in computing from smartphones to datacenters. Improvements originate from the efficient mapping of key inference and training logical operations directly to the physical memory array. The multiply-accumulate operation is physically performed by Kirchoff’s Voltage Law (to multiply an input with a weight) and Kirchoff’s current law (to accumulate column weights) (Fig. 1). The enormous energy expense of moving the data from an arithmetic-logic-unit to a register and back several times per training operation is reduced by a factor roughly proportional to the number of rows (or columns) of a neural network weight matrix (typically >100). Analog array benefits have been well established for the inference stage of neural networks and are now under early commercial development. Harnessing analog arrays for neural network training offers to solve a significantly more energy intensive task than inference only – but analog training remains elusive due to device-level challenges. Training places electrical constraints on the analog memory far beyond those for inference-only accelerators. Foremost among these challenges is obtaining sufficient “linearity” and “symmetry” in analog memory devices. The conductance increments during a weight update operation must occur without feedback to verify the correct conductance change, as this iterative process would negate the energy and latency advances over digital CMOS. This open-loop weight update scheme requires that the analog memory changes a predictable conductance value linearly proportional to the number of write pulses, regardless of the initial state. Hence, this is known as “linearity” of an analog device. The linearity often tends to be differ between the positive and negative conductance increments, indicating poor device "symmetry." Furthermore, devices in an array must have significantly overlapping conductance ranges over many cycles. If the analog memory elements do not have sufficient linearity and symmetry, the neural network will suffer unacceptable accuracy loss during the training stage. This is still an area of active research, with several strong two- and three-terminal candidates. Sandia has developed a characterization methodology and modeling code, CrossSim, which allows the training accuracy to be evaluated for experimental devices. Two terminal emerging memories including oxide-based resistive memory (ReRAM) and phase change memory (PCRAM) are very dense and capable of high speed switching. However, typical TaOx ReRAM and GST PCRAM have been evaluated and found to suffer unacceptable accuracy losses, due to the nonlinearity and asymmetry inherent to the devices. In the case of ReRAM this is most likely due to the nonlinear acceleration of the filament growth these devices when switched from the high conductance to low conductance state, or the abrupt amorphization in the low to high conductance change during the PCRAM RESET process. Recently, three-terminal floating gate semiconductor-oxide-nitride-oxide-semiconductor (SONOS) cell, a close cousin of NAND-flash, have been demonstrated to have high training accuracy, low energy, and may be the best near-term weight storage device. However, challenges of SONOS include the relatively long write latency (>1μs), high voltage, limited scalability, and low endurance. The most novel emerging three terminal class of devices known as nonvolatile redox transistors show excellent training behavior with very low write voltages. These three terminal elements, such as Sandia’s Lithium-Ion Synaptic Transistor for Analog Computing (LISTA), utilize the electrochemical mechanism of a lithium-ion battery, where cathode conductivity is modulated by lithium or proton ion transport (charging and discharging the battery). While very promising, these devices face research challenges of increased speed, endurance, and CMOS integration. This presentation will discuss current research directions for key two- and three-terminal analog neural memory devices, with a focus on areas where materials and device innovation can drive significant process in neural training technology. SNL is managed and operated by NTESS under DOE NNSA contract DE-NA0003525. Figure 1

Modeling the Metal–Insulator Phase Transition in LixCoO2 for Energy and Information Storage

AbstractAn electro‐chemomechanical phase‐field model is developed to capture the metal–insulator phase transformation along with the structural and chemical changes that occur in LixCoO2 in the regular operating range of 0.5 &lt; x &lt; 1. Under equilibrium, in the regime of phase coexistence, it is found that transport limitations lead to kinetically arrested states that are not determined by strain‐energy minimization. Further, lithiation profiles are obtained for different discharging rates and the experimentally observed voltage plateau is observed. Finally, a simple model is developed to account for the conductivity changes for a polycrystalline LixCoO2 thin film as it transforms from the metallic phase to the insulating phase and a strategy is outlined for memristor design. The theory can therefore be used for modeling LixCoO2‐electrode batteries as well as low voltage nonvolatile redox transistors for neuromorphic computing architectures.