Reconvergent Paths Research Articles

Survey on Placement and Routing for Field-Coupled Nanocomputing

CMOS technology is reaching power, thermal, and physical limits at an alarming pace. As a response, post-silicon research investigates alternative technologies to perform computation. Field-Coupled Nanocomputing (FCN) presents low power dissipation, high frequencies, and room temperature operation. Nevertheless, FCN imposes several challenges in the development of efficient and scalable CAD tools. The placement and routing step is especially tricky in FCN compared to CMOS because of synchronization issues inherent to these technologies, such as path balancing and reconvergent paths. In this work, we survey the state-of-art of placement and routing algorithms for FCN. We describe the most recent FCN placement and routing algorithms, highlighting their limitations and, finally, presenting future work directions.

Reconfigurable RO-Path Delay Sensor

In this brief, we propose a method of analyzing signal propagation delay in certain digital circuits and a delay-sensing architecture. Based on controllability probabilities, we present a graph model that is useful for path delay analysis, derivation of test vectors that sensitize paths of interest, and reconvergent path detection. A delay-sensing architecture is illustrated that offers different accuracy levels and provides a nearly-on-the-fly measurement of the delay. The synergy of the introduced model with the introduced architecture is demonstrated by means of an example. The proposed technique can be used for delay estimation, delay characterization and on-demand, real-time, nearly-on-the-fly estimation of the delay of cell-based array logic units, such as multipliers. FPGA measurements show that a better estimation of the delay is possible, compared to simulations, and an increase by 30% of operation frequency is feasible in certain cases, compared to simulation-based frequency estimation.

Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path

Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path

Bit-Width Optimization by Divide-and-Conquer for Fixed-Point Digital Signal Processing Systems

This paper presents a novel approach to fractional bit-width optimization of fixed-point designs. We first propose a divide-and-conquer algorithm that can assign optimal fractional bit-widths to a special class of designs that does not have re-convergent paths starting from an internal signal. General designs are partitioned into designs of that special class and our algorithm is applied to each design. The algorithm recursively breaks down a given design into sub-designs and finds Pareto optimal solutions to each sub-design. Those solutions are merged to form Pareto optimal solutions to a larger design. In addition, two pruning methods based on area and error, respectively, are proposed, speeding up the algorithm. The optimization process is guided by static maximum absolute error analysis, and functional correctness is guaranteed for all possible input stimuli. Our approach is demonstrated in five case studies including polynomial approximation and RGB-to-YCbCr conversion, for which the divide-and-conquer algorithm produces the optimal solutions.

Node-to-node error sensitivity analysis using a graph based approach for VLSI logic circuits

Shrinking the transistors size and supply voltage in the advanced VLSI logic circuits, significantly increases the susceptibility of the circuits to soft errors. Therefore, analysis of the effects on other nodes, caused by the soft errors occurring at each individual node is an essential step for VLSI logic circuit design. In this paper, a novel approach based on the Mason’s gain formula, for the node-to-node sensitivity analysis of logic circuits is proposed. Taking advantage of matrix sparsity, the runtime and the memory requirement of the proposed approach become scalable. Also, taking the effects of reconvergent paths into account, the accuracy of the proposed approach is improved considerably. According to the simulation results, the proposed approach runs 4.7× faster than those proposed in the prior works while its computational complexity is O(N1.07) on the average.

A graph based approach for reliability analysis of nano-scale VLSI logic circuits

Advances in nano-electronics VLSI manufacturing technology and the rapid downscaling of the size of logic circuits have made them more prone to errors. This has led to the need for fast circuit reliability evaluation of large logic circuits. In this paper a new method for reliability analysis of VLSI logic circuits based on a modified form of Mason’s rule is proposed. Utilizing matrix sparsity significantly increases the speed and reduces the required memory of the proposed approach. In addition, an approach is introduced to mitigate the effect of reconvergent paths. Simulation results indicate that the proposed method is scalable and runs 4× faster than previously proposed schemes.

PROBABILISTIC TRANSFER MATRIX WITH MIXED BINARY-DECIMAL CODING FOR LOGIC CIRCUIT RELIABILITY ANALYSIS

Technology scale leads to increasing the vulnerability of new integrated logic circuits. The high-energy neutrons (present in terrestrial cosmic radiation) and alpha particles (that originate from impurities in the packaging materials) play important role in occurrence of transient faults which are effective factor for designing reliable integrated circuits. Thus, a fast and scalable method to obtain accurate reliability value is an issue to have a dependable logic circuit design. In this paper, a new fast and scalable method is proposed to calculate the circuit reliability in which the effects of nested reconvergent paths, as a main source of inaccuracy, is considered. In the presence of reconverging signals a binary probability matrix is used to resolve signals correlation problem and increase the accuracy of the obtained reliability. Also a new mixed binary-decimal code allocation is proposed to increase the scalability of the method and reduce the complexity of calculation. Simulation results show that our proposed solution is a fast method with less complexity and also gives an accurate reliability value in comparison with other methods.

Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA

Reconvergent paths in circuits have been a nuisance in various computer-aided design (CAD) algorithms, but no elegant solution to deal with them has been found yet. In statistical static timing analysis (SSTA), they cause difficulty in capturing topological correlation. This paper presents a technique that in arbitrary block-based SSTA reduces the error caused by ignoring topological correlation. We interpret a timing graph as an algebraic expression made up of addition and maximum operators. We define the division operation on the expression and propose algorithms that modify factors in the expression without expansion. As a result, the algorithms produce an expression to derive the latest arrival time with better accuracy in SSTA. Existing techniques handling reconvergent fanouts usually use dependency lists, requiring quadratic space complexity. Instead, the proposed technique has linear space complexity by using a new directed acyclic graph search algorithm. Our results show that it outperforms an existing technique in speed and memory usage with comparable accuracy. More important, the proposed technique is not limited to SSTA and is potentially applicable to various issues due to reconvergent paths in timing-related CAD algorithms.

A low-power transmission-gate-based 16-bit multiplier for digital hearing aids

The most widespread 16-bit multiplier architectures are compared in terms of area occupation, dissipated energy, and EDP (Energy-Delay Product) in view of low-power low-voltage signal processing for digital hearing aids and similar applications. Transistor-level simulations including back-annotated wire parasitics confirm that the propagation of glitches along uneven and re-convergent paths results in large unproductive node activity. Because of their shorter full-adder chains, Wallace-tree multipliers indeed dissipate less energy than the carry-save (CSM) and other traditional array multipliers (6.0 µW/MHz versus 10.9 µW/MHz and more for 0.25 µm CMOS technology at 0.75 V). By combining the Wallace-tree architecture with transmission gates (TGs), a new approach is proposed to improve the energy efficiency further (3.1 µW/MHz), beyond recently published low-power architectures. Besides the reduction of the overall capacitance, minimum-sized transmission gate full-adders act as RC-low-pass filters that attenuate undesired switching. Finally, minimum size TGs increase the V dd to ground resistance, hence decreasing leakage dissipation (0.55 nW versus 0.84 nW in CSM and 0.94 nW in Wallace).

Postlayout optimization for synthesis of Domino circuits

Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this article, we propose a synthesis scheme to reduce the duplication cost by allowing inverters in Domino logic under certain timing constraints for both simple and complex gates. Moreover, we can include the logic duplication minimization during technology mapping for synthesis of Domino circuits with complex gates. In order to guarantee the robustness of such Domino circuits, we perform the logic optimization as a postlayout step. Experimental results show significant reduction in duplication cost, which translates into significant improvements in area and power. As a byproduct, the timing performance is also improved owing to smaller layout area and/or logic depth.

Delay insertion method in clock skew scheduling

This paper describes a delay insertion method that improves the efficiency of clock skew scheduling. It is shown that reconvergent paths limit the improvement of circuit performance achievable through clock skew scheduling. A delay insertion method is proposed such that the optimal clock period achievable through clock skew scheduling is improved by mitigating the limitations caused by reconvergent paths. Experimental results demonstrate that reconvergent paths are limiting for 34% (41% for level sensitive) of the selected suite of ISCAS'89 benchmark circuits. Through the application of clock skew scheduling with delay insertion, an average improvement of 10% shorter clock periods (9% for level sensitive) is observed for ISCAS'89 benchmark circuits compared to the results of conventional clock skew scheduling.

Area-optimal technology mapping for field-programmable gate arrays based on lookup tables

We present an exact solution to the technology mapping problem for field-programmable gate arrays (FPGAs), where the objective is to minimize the number of lookup tables (LUTs) required to map a logic circuit. The key idea is to compactly formulate the mapping problem as a mixed-integer linear-programming (MILP) problem, which can then be solved by any off-the-shelf MILP solver. MILP problem formulations are systematically developed for various classes of circuits with increasing complexities-trees, monotone circuits, and general nonmonotone circuits, where the monotonicity of a circuit implies that the number of signals increases monotonically as the circuit is traversed from primary outputs to primary inputs. Several circuit properties related to reconvergent paths and monotone signal sets are determined, which provide insight into the mapping problem for LUTs. Our experiments show that optimal mappings for circuits with several hundred gates can be obtained very quickly by solving their MILP formulations exactly. For larger circuits, we present two powerful heuristic approximation methods based on partitioning the circuit or simplifying its structure. We show that these approximations yield near-optimal solutions for several benchmark circuits.

Power Estimation Using Probability Polynomials

We describe a method of polynomial simulation to calculate switching activities in a general-delay logic circuit. This method is a generalization of the exact signal probability evaluation method due to Parker and McCluskey, which has been extended to handle temporal correlation and arbitrary transport delays. The method can target both combinational and sequential circuits. Our method is parameterized by a single parameter l, which determines the speed-accuracy tradeoff. l indicates the depth in terms of logic levels over which spatial signal correlation is taken into account. This is done by only taking into account reconvergent paths whose length is at most l. The rationale is that ignoring spatial correlation for signals that reconverge after many levels of logic introduces negligible error. When l = L, where L is the total number of levels of logic in the circuit, the method will produce the exact switching activity under a zero delay model, taking into account all internal correlation. We present results that show that the error in the switching activity and power estimates is very small even for small values of l. In fact, for most of the examples, power estimates with l = 0 are within 5% of the exact. However, this error can be higher than 20% for some examples. More robust estimates are obtained with l = 2, providing a good compromise between speed and accuracy.

Partial bist insertion to eliminate data correlation

A new partial BIST insertion approach based on eliminating data correlation to improve pseudo-random testability is presented. Data correlation causes the circuit to be in a subset of the states more or less frequently, which leads to low fault coverage in pseudo-random test. One important cause of correlation is reconvergent fanout. Incorporating BIST test flip-flops into reconvergent paths will break correlation, however, breaking all reconvergent fanout is unnecessary since some reconvergent fanout results in negligible correlation. We introduce a metric to determine the degree of correlation caused by a set of reconvergent fanout paths. We use this metric to identify problematic reconvergent fanout which must be broken through partial BIST insertion. We provide an algorithm to break high correlation reconvergent paths. Our algorithm provides high fault coverage while selecting fewer BIST flip-flops than required using loop breaking techniques. Experimental results produced using our algorithm rank on average among the top 11.6% of all possible solutions with the same number of flip-flops.

재수렴성 경로를 고려한 견실한 신호 전이 밀도 예측

전력 소모 예측에 필요한 신호 전이 밀도를 구하기 위하여, 제로 지연 모델에 대한 견실한 신호 전이 밀도 전파 방법이 제시된다. 제로 기연 모델을 위한 전력 예측은 전력 소모의 하한 경계값을 위한 적절한 기준이다. 입력 특성이 일반적으로 설계 단계에 알려져 있지 않기 때문에 광범위한 입력 특성에 대한 견실한 예측은 전력 소모에 대하여 매우 중요하다. 본 연구에서는 기존의 신호 전이 예측 방법에 대하여 입력 및 출력의 변이 특성을 분석하고 이러한 분석 결과에 근거하여 새로운 견실한 신호 전이 밀도 전파 방법을 제안한다. 실제 회로에 적용하기 위하여 전력 예측의 정확성에 크게 영향을 미치는 재수렴성 경로를 고려한 알고리즘을 제안 및 연구한다. 실험에 의하면 제안한 방법이 기존의 방법과 비교할 때 더욱 양호한 견실성 및 종래의 방식에 상응하는 정확성과 경과 시간을 보여준다. A robust signal transition density propagation method for a zero delay model is presented to obtain the signal transition density for estimating the power consumption. The power estimation for the zero delay model is a proper criteria for the lower boundary of power consumption. Since the input characteristics are generally unknown at design stage, robust estimation for wide range input characteristics is very important for the power consumption. In this paper, a conventional transition estimation method will be explored. And this exploration will be analyzed with the input/output signal transition behavior and used to propose the robust signal transition density propagation for the power estimation. In order to apply to practical circuits, the reconvergent path, which is crucial to affect the exactness of the power estimation, will be studied and an algorithm to take the reconvergent path into consideration will be presented. In experiment, the proposed methodology shows better robustness, comparable accuracy and elapsed time compared to the conventional methods.

Efficient algorithm for untestable path detection

The authors present an algorithm for detecting untestable paths in multi-level circuits. By constructing equivalent normal form (ENF) for reconvergent paths only, the proposed algorithm detects and removes untestable paths efficiently in terms of run-time and memory usage.

Performance-oriented technology mapping for LUT-based FPGA's

An efficient and effective optimization technique is developed for technology mapping of lookup table (LUT) based field programmable gate arrays. In our algorithm, minimal depth of a Boolean network is found and then the given cost function is minimized by nodes of the given Boolean network without increasing the depth. The sweeping allows an efficient search over a huge solution space since it utilizes the topological structure of the network. Optimization for reconvergent paths and duplication of logic can be automatically considered during the sweeping procedure. Experimental results show that our approach is very promising. Typically our method, called SWEEP, produced the same depth for the 17 benchmark circuits tried as those of FlowMap which guarantees the optimum depth. Furthermore, SWEEP outperforms FlowMap by 17% in the total number of LUT's required to implement the benchmark circuits. >