Reconfigurable RO-Path Delay Sensor

Abstract

In this brief, we propose a method of analyzing signal propagation delay in certain digital circuits and a delay-sensing architecture. Based on controllability probabilities, we present a graph model that is useful for path delay analysis, derivation of test vectors that sensitize paths of interest, and reconvergent path detection. A delay-sensing architecture is illustrated that offers different accuracy levels and provides a nearly-on-the-fly measurement of the delay. The synergy of the introduced model with the introduced architecture is demonstrated by means of an example. The proposed technique can be used for delay estimation, delay characterization and on-demand, real-time, nearly-on-the-fly estimation of the delay of cell-based array logic units, such as multipliers. FPGA measurements show that a better estimation of the delay is possible, compared to simulations, and an increase by 30% of operation frequency is feasible in certain cases, compared to simulation-based frequency estimation.