Reconfiguration Overhead Research Articles

Performance Analysis of Optical Packet Switches with Reconfiguration Overhead

In optical packet switches, the overhead of reconfiguring a switch fabric is not negligible with respect to the packet transmission time and can adversely affect switch performance. The overhead increases the average waiting time of packets and worsens throughput performance. Therefore, scheduling packets requires additional considerations on the reconfiguration frequency. This work intends to analytically find the optimal reconfiguration frequency that minimizes the average waiting time of packets. It proposes an analytical model to facilitate our analysis on reconfiguration optimization for input-buffered optical packet switches with the reconfiguration overhead. The analytical model is based on a Markovian analysis and is used to study the effects of various network parameters on the average waiting time of packets. Of particular interest is the derivation of closed-form equations that quantify the effects of the reconfiguration frequency on the average waiting time of packets. Quantitative examples are given to show that properly balancing the reconfiguration frequency can significantly reduce the average waiting time of packets. In the case of heavy traffic, the basic round-robin scheduling scheme with the optimal reconfiguration frequency can achieve as much as 30% reduction in the average waiting time of packets, when compared with the basic round-robin scheduling scheme with a fixed reconfiguration frequency.

Floorplanning for Partially Reconfigurable FPGAs

Partial reconfiguration on heterogeneous field-programmable gate arrays with millions of gates yields better utilization of its different types of resources by swapping in and out the appropriate modules of one or more applications at any instant of time. Given a schedule of sub-task instances where each instance is specified as a netlist of active modules, reconfiguration overhead can be reduced by fixing the position and shapes of modules common across all instances. We propose a global floorplan generation method PartialHeteroFP to obtain same positions for the common modules across all instances such that the heterogeneous resource requirements of all modules in each instance are satisfied, and the total half-perimeter wirelength over all instances is minimal. Experimental results establish that the proposed PartialHeteroFP produces floorplans very fast, with 100% match of common modules and thereby minimizing the partial reconfiguration overhead.

A Parallelization Cost Model for FPGA

Using FPGA for general-purpose computing has become an important research direction in high performance computing technology. However, it is not a lossless optimization method. Due to the impact of hardware reconfiguration overhead, data transmission cost, specific characteristics of programs, and other factors, the speedup of general-purpose computing on FPGA has visible difference. On the basis of in-depth analysis of FPGA architecture and development process, the main factors affecting FPGA implementation performance are pointed out, and a parallel cost model for FPGA based on static program analysis is proposed to provide judgment basis for using FPGA in general-purpose computing. The experiment results show that the algorithm estimates accurately FPGA execution performance.

A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback

Dynamically reconfigurable computing platforms provide promising methods for dynamic management of hardware resources, power, and performance. Yet, progress in dynamically reconfigurable computing is fundamentally limited by the reconfiguration time overhead. Prior research in the development of dynamic partial reconfiguration (DPR) controllers has been limited by its use of the Processor Local Bus (PLB). As a result, the bus was unavailable during DPR. This resulted in significant time overhead. To minimize the overhead, we introduce the use of a multiport memory controller (MPMC) that frees the PLB during the reconfiguration process. The processor is thus allowed to switch to other tasks during the reconfiguration operation. This effectively limits the reconfiguration overhead. An interrupt is used to inform the processor when the operation is complete. Therefore, the system can multitask during the reconfiguration operation. Furthermore, to maximize performance, we introduce the use of overclocking with active feedback. During overclocking, the use of active feedback is used to ensure that the device voltage and temperature are within nominal operating conditions. All of these contributions lead to significant performance improvements over current partial reconfiguration subsystems. The portability of the system, demonstrated on the Virtex-4 and the Virtex-5, consists of four different hardware platforms.

Fingerprint Image Processing Acceleration Through Run-Time Reconfigurable Hardware

To the best of the authors' knowledge, this is the first brief that implements a complete automatic fingerprint-based authentication system (AFAS) application under a dynamically partial self-reconfigurable field-programmable gate array (FPGA). The main benefits of this implementation are the acceleration of the processing reached by the parallelism inherent to the hardware design, the high level of integration, the consequent security and reliability improvements provided by the usage of a system-on-programmable-chip device that is able to embed the main components of the application in a single chip, and the low cost achieved by the whole system due to the reconfigurability performance featured by the suggested FPGA. All these factors result in an outstanding system that is able to authenticate the identity of any user by means of those distinctive characteristics available in fingerprints. This brief reveals the advantages of run-time reconfigurable hardware in the implementation of those embedded systems demanding real-time performance at low cost. The minimization of the reconfiguration overhead by means of the proper sizing of the reconfigurable region in the FPGA and the design of a hardware configuration controller that is able to reach the maximum configuration rates allowed by the technology (3.2 Gb/s) are key factors to succeed in the development of the embedded AFAS application. The proposed system, which is implemented by means of hardware-software co-design techniques under a Virtex4 XC4VLX25 FPGA working at 100 MHz, is able to overcome in one order of magnitude the execution time performance achieved by a personal computer platform based on an Intel Core2Duo microprocessor running at 1.83 GHz.

Biometrics-based consumer applications driven by reconfigurable hardware architectures

Nowadays the development of automatic biometrics-based personal recognition systems is a reality in the current technological age. Not only those applications demanding stringent security levels but also many daily use consumer applications request the existence of high performance computational platforms in charge of recognizing the identity of an individual based on the analysis of his/her physiological or behavioural characteristics. The state of the art points out two main open problems in the implementation of such automatic applications: on the one hand, the needed improvement of the reliability level of the existing recognition systems in terms of accuracy, security and real-time performances; on the other hand, the cost reduction of those physical platforms in charge of the processing. This work addresses those limitations of current systems and aims at finding the proper system architecture to develop this kind of high-performance applications at low cost. Because of that, those existing solutions based on expensive multiprocessor systems like HPC (High Performance Computer), GPU (Graphics Processing Unit), or PC (Personal Computer) platforms need to be discarded, and instead of them embedded system solutions based on programmable logic devices are suggested in this work. The programmability performances of FPGA (Field Programmable Gate Array) devices together with the inherent parallelism of hardware design provide the needed flexibility to develop made-to-measure coprocessors in charge of accelerating those time-critical computational tasks. To address the cost of the system, dynamically reconfigurable FPGAs are suggested in this work. The scheduling of the recognition application into a series of mutually exclusive tasks, and the reutilization of those functional resources available in the FPGA by multiplexing different coprocessors in the same area along the application execution time allows reducing the size of the device and therefore its cost at the expense of the reconfiguration overhead. The hardware–software co-design of an AFAS (automatic fingerprint-based authentication system) under two different run-time reconfigurable platforms is presented as the proof of concept of the suggested architecture. The outstanding results achieved in this work pave the way for the implementation of biometric applications by means of run-time reconfigurable FPGAs.

A context-aware reflective middleware framework for distributed real-time and embedded systems

Context-aware reflective middleware (CARM), which supports application reconfiguration, has been an appealing technique for building distributed real-time and embedded (DRE) systems as it can adapt their behaviors to changing environments at run time. However, existing CARM frameworks impose dependence restrictions and reconfiguration overhead, which makes the reconfiguration time of these frameworks too long (normally in the range of seconds or more) to satisfy the stringent real-time requirements of DRE systems. To improve the reconfiguration efficiency for supporting DRE systems, we have designed a new CARM framework – MARCHES (Middleware for Adaptive Robust Collaborations across Heterogeneous Environments and Systems), which offers an original structure of multiple component chains to reduce local behavior change time and a novel synchronization protocol using active messages to reduce distributed behavior synchronization time. MARCHES uses a layered architecture and provides both component-level and system-level reflection to incorporate standard components, a hierarchical event notification model to evaluate contexts, and a lightweight XML-based script language to describe and manage adaptation policies. The MARCHES framework and supported applications have been implemented on PC and PDA platforms. Based on a novel theoretical model, we have analyzed the reconfiguration efficiency of MARCHES and compared it with those of peer CARM frameworks: MobiPADS and CARISMA. Quantitative empirical results show that the reconfiguration time of MARCHES is reduced from seconds to hundreds of microseconds. Evaluations demonstrate that MARCHES is robust, scalable and generates a small memory footprint, which makes it suitable for supporting DRE systems.

The design and implementation of service process reconfiguration with end-to-end QoS constraints in SOA

Service processes in SOA are composed dynamically by services from different service providers. At run-time, some services may become faulty and cause a service process to violate its end-to-end quality of service (QoS) constraints. We propose an effective approach for replacing only faulty services and some of their neighboring services to maintain the original end-to-end QoS constraints. We use an iterative algorithm to search for a reconfiguration region that has replaceable services to meet the original QoS constraint for the region. Services in reconfiguration regions may be replaced using one-to-one, one-to-many, or many-to-one service mappings. By replacing only services in reconfiguration regions rather than the whole service process, reconfiguration overheads are lowered and service disruptions may be reduced. We have implemented the Adaptation Manager in the Llama ESB middleware. Performance study shows that our approach may efficiently repair service processes.

Configuration Locking and Schedulability Estimation for Reduced Reconfiguration Overheads of <newline/>Reconfigurable Systems

Dynamically reconfigurable field-programmable gate arrays (FPGAs) hold the promise of providing a virtual hardware resource in which hardware circuits can be dynamically scheduled onto the available FPGA resources. However, reconfiguring an FPGA can incur significant performance and energy overheads. This paper analyzes the relationship between several hardware task scheduling algorithms and their impact on the number of reconfigurations required to execute a set of hardware tasks. In addition, three new hardware scheduling algorithms, specifically designed to reduce the number of required reconfigurations, are presented and analyzed. By selectively locking configurations within the reconfigurable tiles of an FPGA, significant reductions in the number of required reconfiguration can be achieved.

Service de reconfiguration prédictif pour plateforme multicoeur hétérogène

This article describes a dynamic reconfiguration management service, named PCM, targeting heterogeneous multicore architectures, composed of reconfigurable or programmable cores of different kind. The goal is to hide, from the execution point of view, the loading time of bitstreams into the cores of the reconfigurable system. For that, the PCM uses predictive prefetch techniques based on static analysis of the application and the current behavior of the execution. This new functionality allows a better usage of the reconfigurable resources of the system. A software implementation of the prefetch service and its functional validation are presented. The platform architecture of the Morpheus european project is used as an example for this validation: we show how to hide the overhead of reconfiguration on application graphs.

A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations

Signal processors exploiting ASIC acceleration suffer from sky-rocketing manufacturing costs and long design cycles. FPGA-based systems provide a programmable alternative for exploiting computation parallelism, but the flexibility they provide is not as high as in processor-oriented architectures: HDL or C-to-HDL flows still require specific expertise and a hardware knowledge background. On the other hand, the large size of the configuration bitstream and the inherent complexity of FPGA devices make their dynamic reconfiguration not a very viable approach. Coarse-grained reconfigurable architectures (CGRAs) are an appealing solution but they pose implementation problems and tend to be application specific. This paper presents a scalable CGRA which eases the implementation of algorithms on field programmable gate array (FPGA) platforms. This design option is based on two levels of programmability: it takes advantage of performance and reliability provided by state-of-the-art FPGA technology, and at the same time it provides the user with flexibility, performance and ease of reconfiguration typical of standard CGRAs. The basic cell template provides advanced features such as sub-word SIMD integer and floating-point computation capabilities, as well as saturating arithmetic. Multiple reconfiguration contexts and partial run-time reconfiguration capabilities are provided, tackling this way the problem of high reconfiguration overhead typical of FPGAs. Selected instances of the proposed architecture have been implemented on an Altera Stratix II EP2S180 FPGA. On this system, we mapped some common DSP, image processing, 3D graphics and audio compression algorithms in order to validate our approach and to demonstrate its effectiveness by benchmarking the benefits achieved.

A Closed-Loop Control Traffic Engineering System for the Dynamic Load Balancing of Inter-AS Traffic

Inter-AS outbound traffic engineering (TE) is a set of techniques for controlling inter-AS traffic exiting an autonomous system (AS) by assigning the traffic to the best egress points (i.e. routers or links) from which the traffic is forwarded to adjacent ASes towards the destinations. In practice, changing network conditions such as inter-AS traffic demand variation, link failures and inter-AS routing changes occur dynamically. These changes can make fixed outbound TE solutions inadequate and may subsequently cause inter-AS links to become congested. In order to overcome this problem, we propose the deployment of a closed-loop control traffic engineering system that makes outbound traffic robust to inter-AS link failures and adaptive to changing network conditions. The objective is to keep the inter-AS link utilization balanced under unexpected events while reducing service disruptions and reconfiguration overheads. Our evaluation results show that the proposed system can successfully achieve better load balancing with less service disruption and re-configuration overhead in comparison to alternative approaches.

Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration

In this article, we propose field programmable gate array-based scalable architecture for discrete cosine transform (DCT) computation using dynamic partial reconfiguration. Our architecture can achieve quality scalability using dynamic partial reconfiguration. This is important for some critical applications that need continuous hardware servicing. Our scalable architecture has three features. First, the architecture can perform DCT computations for eight different zones, that is, from 1 × 1 DCT to 8× 8 DCT. Second, the architecture can change the configuration of processing elements to trade off the precisions of DCT coefficients with computational complexity. Third, unused PEs for DCT can be used for motion estimation computations. Using dynamic partial reconfiguration with 2.3MB bitstreams, 80 distinct hardware architectures can be implemented. We show the experimental results and comparisons between different configurations using both partial reconfiguration and nonpartial reconfiguration process. The detailed trade-offs among visual quality, power consumption, processing clock cycles, and reconfiguration overhead are analyzed in the article.

Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs

As technology continues to shrink, reducing leakage power of Field-Programmable Gate Arrays (FPGAs) becomes a critical issue for the practical use of FPGAs. In this article, we address the leakage issue of partially dynamically reconfigurable FPGA architectures with sleep transistors embedded into FPGA fabrics. In particular, we focus on eliminating leakage waste due to the delay between reconfiguration and execution time of a task. For partially dynamically reconfigurable FPGAs, the configuration prefetching technique is commonly used to hide runtime reconfiguration overhead. With prefetching, the configuration of a task is loaded into FPGAs as early as possible. Therefore, there is often a delay between reconfiguration and execution time of a task. In this period of time, the SRAM cells allocated to a task cannot be turned off even though they are not utilized. In this article, we propose a two-stage task scheduling methodology to reduce leakage waste due to the delay between reconfiguration and execution time of a task without sacrificing performance. In the first stage, a performance-driven task scheduler that targets at minimizing the schedule length is invoked to generate an initial placement. In the second stage, a postplacement leakage-aware task scheduling is applied to refine the initial placement such that leakage waste is minimized provided that the schedule length is not increased. To solve the postplacement leakage optimization problem, we propose two algorithms. The first one is an optimal algorithm based on Integer Linear Programming (ILP). The second algorithm is a heuristic approach that iteratively refines the placement to reduce leakage waste. Experimental results on real and synthetic designs show that the efficiency and effectiveness of the proposed postplacement leakage reduction techniques.

Minimum Delay Scheduling for Performance Guaranteed Switches With Optical Fabrics

We consider traffic scheduling in performance guaranteed switches with optical fabrics to ensure 100% throughput and bounded packet delay. Each switch reconfiguration consumes a constant period of time called reconfiguration overhead, during which no packet can be transmitted across the switch. To minimize the packet delay bound for an arbitrary traffic matrix, the number of switch configurations in the schedule should be no larger than the switch size N . This is called minimum delay scheduling, where the ideal minimum packet delay bound is determined solely by the total overhead of the N switch reconfigurations. A speedup in the switch determines the actual packet delay bound, which decreases toward the ideal bound as the speedup increases. Our objective is to minimize the required speedup S schedule under a given actual packet delay bound. We propose a novel minimum delay scheduling algorithm quasi largest-entry-first (QLEF) to solve this problem. Compared with the existing minimum delay scheduling algorithms MIN and alphai-SCALE, QLEF dramatically cuts down the required S schedule bound. For example, QLEF only requires S schedule=17.89 for N=450, whereas MIN and alphai -SCALE require S schedule=37.13 and 27.82, respectively. This gives a significant performance gain of 52% over MIN and 36% over alphai-SCALE.

Minimizing Internal Speedup for Performance Guaranteed Switches With Optical Fabrics

We consider traffic scheduling in an N times N packet switch with an optical switch fabric, where the fabric requires a reconfiguration overhead to change its switch configurations. To provide 100% throughput with bounded packet delay, a speedup in the switch fabric is necessary to compensate for both the reconfiguration overhead and the inefficiency of the scheduling algorithm. In order to reduce the implementation cost of the switch, we aim at minimizing the required speedup for a given packet delay bound. Conventional Birkhoff-von Neumann traffic matrix decomposition requires N2 - 2N + 2 configurations in the schedule, which lead to a very large packet delay bound. The existing DOUBLE algorithm requires a fixed number of only 2N configurations, but it cannot adjust its schedule according to different switch parameters. In this paper, we first design a generic approach to decompose a traffic matrix into an arbitrary number of Ns (N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> - 2N + 2 > N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> > N) configurations. Then, by taking the reconfiguration overhead into account, we formulate a speedup function. Minimizing the speedup function results in an efficient scheduling algorithm ADAPT. We further observe that the algorithmic efficiency of ADAPT can be improved by better utilizing the switch bandwidth. This leads to a more efficient algorithm SRF (scheduling residue first). ADAPT and SRF can automatically adjust the number of configurations in a schedule according to different switch parameters. We show that both algorithms outperform the existing DOUBLE algorithm.

Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations

Partial dynamic reconfiguration, often called run-time reconfiguration (RTR), is a key feature in modern reconfigurable platforms. In this paper, we present parallelism granularity selection (PARLGRAN), an application mapping approach that maximizes performance of application task chains on architectures with such capability. PARLGRAN essentially selects a suitable granularity of data-parallelism for individual data parallel tasks while considering key issues such as significant reconfiguration overhead and placement constraints. It integrates granularity selection very effectively in a joint scheduling and placement formulation, necessary due to constraints imposed by partial RTR. As a key step to validating PARLGRAN, we additionally present an exact strategy (integer linear programming formulation). We demonstrate that PARLGRAN generates high-quality schedules with: (1) a set of small test cases where we compare our results with the exact strategy; (2) a very large set of synthetic experiments with over a thousand data-points where we compare it with a simpler strategy that tries to statically maximize data-parallelism, i.e., only considers resource availability; and (3) a detailed application case study of JPEG encoding. The application case-study confirms that blindly maximizing data-parallelism can result in schedules even worse than that generated by a simple (but RTR-aware) approach oblivious to data-parallelism. Last, but very important, we demonstrate that our approach is well-suited for true on-demand computing with detailed execution time estimates on a typical embedded processor. Heuristic execution time is comparable to task execution time, i.e., it is feasible to integrate PARLGRAN in a run-time scheduler for dynamically reconfigurable architectures.

Dynamic reconfiguration architectures for multi-context FPGAs

Field-programmable gate arrays (FPGAs) are being integrated with processors on the same motherboard or even chip in order to achieve flexible high-performance computing, and this may become main stream in chip multi-core architectures. However, the expensive FPGA area is often used inefficiently, with much of the logic idle at any given time. This work, motivated by the Dynamic-Link Library (DLL) concept in software, explores the possibility of “hardware DLLs” by finding ways for fast dynamic incremental reconfiguration of FPGAs. So doing would, among other things, enable same-function replication at any given time, with functions changing quickly over time, thereby enabling efficient exploitation of data parallelism at no additional hardware cost. We present two new multi-context FPGA architectures based on two different configuration storage architectures: local and centralized. Problems such as configuration storage and reconfiguration (time, power and space) overhead are considered. Well known area and power models are used in evaluating various approaches and in order to provide guidelines for matching architectures to target applications. Lastly, we provide insights into resulting scheduling issues. Our findings provide the foundation and “rules of the game” for subsequent development of reconfiguration schedulers and execution environments.

Customized kernel execution on reconfigurable hardware for embedded applications

To conserve space and power as well as to harness high performance in embedded systems, high utilization of the hardware is required. This can be facilitated through dynamic adaptation of the silicon resources in reconfigurable systems in order to realize various customized kernels as execution proceeds. Fortunately, the encountered reconfiguration overheads can be estimated. Therefore, if the scheduling of time-consuming kernels considers also the reconfiguration overheads, an overall performance gain can be obtained. We present our policy, experiments, and performance results of customizing and reconfiguring Field-Programmable Gate Arrays (FPGAs) for embedded kernels. Experiments involving EEMBC (EDN Embedded Microprocessor Benchmarking Consortium) and MiBench embedded benchmark kernels show high performance using our main policy, when considering reconfiguration overheads. Our policy reduces the required reconfigurations by more than 50% as compared to brute-force solutions, and performs within 25% of the ideal execution time while conserving 60% of the FPGA resources. Alternative strategies to reduce the reconfiguration overhead are also presented and evaluated.

Reducing Reconfiguration Overheads in Heterogeneous Multicore RSoCs with Predictive Configuration Management

A predictive dynamic reconfiguration management service is described here, targeting a new generation of multicore SoC that embed multiple heterogeneous reconfigurable cores. The main goal of the service is to hide the reconfiguration overheads, thus permitting more dynamicity for reconfiguring. We describe the implementation of the reconfiguration service managing three heterogeneous cores; functional results are presented on generated multithreaded applications.