A parallel processing system is described based on a number of microprocessor nodes interconnected by means of reconfigurable, reallocatable blocks of memory. The ideas presented address what the authors perceive as the drawbacks of current parallel microprocessor architectures such as transputer based systems. The concepts presented are applicable to a broad range of microprocessors and application areas. The system offers minimal communications latency between any arbitrary pair of processors in the system. Communicating processors are connected via a communications path on a point to point basis. The interconnection network is inherently reconfigurable. Reconfiguration occurs with no apparent overhead to the processor nodes. Communication paths between the processor nodes are implemented by shared memory blocks which, combined with dynamic reconfiguration and reallocation, overcome the bus bandwidth problem normally associated with shared memory architectures. Strategies for scaling the architecture are discussed. A working prototype of the system based on widely available, low-cost, off-the-shelf components demonstrates the feasibility of the architecture. Some preliminary performance figures are presented.