Reconfigurable Parallel Processing Research Articles

Optimised Implementation of Dense Stereo Correspondence for Resource Limited Hardware

Computer stereo vision is a passive sensing technique that helps to recover 3D information of an environment from 2D images. The stereo correspondence is a challenging task that finds out matching pixels between the stereo image pair based on Lambertian criteria and its result is a disparity space image. The depth of the objects from the camera can be calculated from this disparity value by using the principle of triangulation. For the vision guided robot navigation, the requirement of stereo matching algorithms on low power dedicated hardware that can achieve a high frame rate is unambiguous. A new, highly optimized implementation of correlation based, Sum of Absolute Differences correspondences algorithm on a low cost resource limited FPGA is presented here. This System-on-Programmable-Chip architecture based system achieved a higher frame rate of 50 fps with 64 disparity levels without using a microprocessor. On performance evaluation, the disparity map shows a maximum error of 0.308% only. This reconfigurable parallel processing, high speed architecture of the algorithm implementation takes only 43% of available resources of low density Altera Cyclone II. This hardware implementation of stereo vision system outperforms in terms of accuracy, speed and resource utilization of all the other existing stereo systems of its similar kind. Also, it offers a better trade-off between run-time speed and accuracy and is found suitable for most of the range finding real-time applications.

A holistic approach for tightly coupled reconfigurable parallel processors

New standards in signal, multimedia, and network processing for embedded electronics are characterized by computationally intensive algorithms, high flexibility due to the swift change in specifications. In order to meet demanding challenges of increasing computational requirements and stringent constraints on area and power consumption in fields of embedded engineering, there is a gradual trend towards coarse-grained parallel embedded processors. Furthermore, such processors are enabled with dynamic reconfiguration features for supporting time- and space-multiplexed execution of the algorithms. However, the formidable problem in efficient mapping of applications (mostly loop algorithms) onto such architectures has been a hindrance in their mass acceptance. In this paper we present (a) a highly parameterizable, tightly coupled, and reconfigurable parallel processor architecture together with the corresponding power breakdown and reconfiguration time analysis of a case study application, (b) a retargetable methodology for mapping of loop algorithms, (c) a co-design framework for modeling, simulation, and programming of such architectures, and (d) loosely coupled communication with host processor.

Optimal algorithms for the channel-assignment problem on a reconfigurable array of processors with wider bus networks

The computation model on which the algorithms are developed is the reconfigurable array of processors with wider bus networks (abbreviated to RAPWBN). The main difference between the RAPWBN model and other existing reconfigurable parallel processing systems is that the bus width of each network is bounded within the range [2,[/spl radic/(N)]]. Such a strategy not only saves the silicon area of the chip as well as increases the computational power enormously, but the strategy also allows the execution speed of the proposed algorithms to be tuned by the bus bandwidth. To demonstrate the computational power of the RAPWBN, the channel-assignment problem is derived in this paper. For the channel-assignment problem with N pairs of components, we first design an O(T + [N//spl omega/]) time parallel algorithm using 2N processors with a 2N-row by 2N-column bus network, where the bus width of each bus network is /spl omega/-bit for 2 /spl les/ /spl omega/ /spl les/ [/spl radic/N] and T = [log/sub /spl omega//N] + 1. By tuning the bus bandwidth to the natural log N-bit and the extended N/sup 1/c/-bit (N/sup 1/c/ > log N) for any constant c and c /spl ges/ 1, two more results which run in O(log N/log log N) and O(1) time, respectively, are also derived. When compared to the algorithms proposed by Olariu et al. [17] and Lin [14], it is shown that our algorithm runs in the equivalent time complexity while significantly reducing the number of processors to O(N).

Reconfigurable parallel VLSI processor for dynamic control of intelligent robots

In the sensor feedback control of intelligent robots, the delay time must be reduced for a large number of multiply-additions. To reduce the delay time for multi-operand multiply additions, the architecture of the reconfigurable parallel processor is proposed. In each PE, a switch circuit (SC) is used to change the connection between multipliers and adders. By changing the switch elements in the SC using the very-long-instruction-word (VLIW) control method, the multiply-adders having desired numbers of multipliers can be reconfigured every clock cycle. Since the data transfer is performed by the direct connection between multipliers and adders, the overhead for data transfer is greatly reduced. In addition, the utilised ratio of the multipliers and the adders is increased. The chip evaluation based on 0.8 /spl mu/m CMOS design rule shows that the delay time for dynamic control of a seven-degrees-of-freedom (DOF) redundant robot manipulator becomes about 10 /spl mu/s which is about 7.7 times faster than that of a parallel-processor approach using conventional digital signal processors (DSPs).

Implementing regularly structured neural networks on the DREAM machine

High-throughput implementations of neural network models are required to transfer the technology from small prototype research problems into large-scale "real-world" applications. The flexibility of these implementations in accommodating for modifications to the neural network computation and structure is of paramount importance. The performance of many implementation methods today is greatly dependent on the density and the interconnection structure of the neural network model being implemented. A principal contribution of this paper is to demonstrate an implementation method which exploits maximum amount of parallelism from neural computation, without enforcing stringent conditions on the neural network interconnection structure, to achieve this high implementation efficiency. We propose a new reconfigurable parallel processing architecture, the Dynamically Reconfigurable Extended Array Multiprocessor (DREAM) machine, and an associated mapping method for implementing neural networks with regular interconnection structures. Details of the system execution rate calculation as a function of the neural network structure are presented. Several example neural network structures are used to demonstrate the efficiency of our mapping method and the DREAM machine architecture on implementing diverse interconnection structures. We show that due to the reconfigurable nature of the DREAM machine, most of the available parallelism of neural networks can be efficiently exploited.

Genetic algorithm for mapping tasks onto a reconfigurable parallel processor

The authors describe a genetic algorithm for a difficult optimisation problem which arises in the context of parallel processing. The problem is to assign each task in the given task graph T to a processor, so as to minimise the total overall execution time of the tasks. Total execution time is computed with the knowledge of individual run times of tasks and the communication requirements among tasks. The intertask communication time is dependent on the interconnection network which connects the processors. No prior knowledge of the interconnection topology is assumed. The algorithm finds the interconnection architecture that is best suited for the task graph T; this makes sense when the target architecture is reconfigurable through programmable switches, e.g. transputer based parallel processors. The algorithm is also extended to add heterogeneous platforms, where each task t can be executed on a particular class of processors. The optimisation technique is based on the genetic paradigm. The authors describe an efficient chromosome representation, genetic operators and a fitness measure suitable for the application.

再構成可能並列プロセッサと知能ロボット制御への応用

In the sensor feedback control of intelligent robots, the delay time must be reduced for a large number of arithmetic operations. In addition to many multiply-additions, the arithmetic operations such as absolute value calculation and maximum value selection are often used in the dynamic control of robot manipulators. To reduce the delay time for multi-operand arithmetic operations, the architecture of the reconfigurable parallel processor is proposed. In each processor element, a switch circuit is used to change the connection between the multipliers, adders and arithmetic units (AUs), so that the multi-operand AUs having desired numbers of operands can be reconfigured. Since the data transfer is accomplished by the direct connection between the multipliers, adders and AUs, the overhead for data transfer is reduced. The chip evaluation based on 0.8 [μm] CMOS design rule shows that the delay time for differential inverse kinematics computation and inverse dynamics computation of a six-degrees-of freedom manipulator become 1.7 [μsec] and 11.5 [μsec], respectively.

A dynamically reconfigurable parallel processing system

A parallel processing system is described based on a number of microprocessor nodes interconnected by means of reconfigurable, reallocatable blocks of memory. The ideas presented address what the authors perceive as the drawbacks of current parallel microprocessor architectures such as transputer based systems. The concepts presented are applicable to a broad range of microprocessors and application areas. The system offers minimal communications latency between any arbitrary pair of processors in the system. Communicating processors are connected via a communications path on a point to point basis. The interconnection network is inherently reconfigurable. Reconfiguration occurs with no apparent overhead to the processor nodes. Communication paths between the processor nodes are implemented by shared memory blocks which, combined with dynamic reconfiguration and reallocation, overcome the bus bandwidth problem normally associated with shared memory architectures. Strategies for scaling the architecture are discussed. A working prototype of the system based on widely available, low-cost, off-the-shelf components demonstrates the feasibility of the architecture. Some preliminary performance figures are presented.

Data management and control-flow aspects of an SIMD/SPMD parallel language/compiler

Features of an explicitly parallel programming language targeted for reconfigurable parallel processing systems, where the machine's N processing elements (PEs) are capable of operating in both the SIMD and SPMD modes of parallelism, are described. The SPMD (single program-multiple data) mode of parallelism is a subset of the MIMD mode where all processors execute the same program. By providing all aspects of the language with an SIMD mode version and an SPMD mode version that are syntactically and semantically equivalent, the language facilitates experimentation with and exploitation of hybrid SIMD/SPMD machines. Language constructs (and their implementations) for data management, data-dependent control-flow, and PE-address-dependent control-flow are presented. These constructs are based on experience gained from programming a parallel machine prototype and are being incorporated into a compiler under development. Much of the research presented is applicable to general SIMD machines and MIMD machines. >

Dynamic intelligent scheduling and control of reconfigurable parallel architectures for computer vision/image processing

This paper presents a system for dynamic intelligent scheduling and control of reconfigurable parallel processors. The purpose of the system is to provide a rapid prototyping capability for computer vision/image processing tasks. The scheduler particularly addresses the problems of algorithms with execution times that depend on the image data and processing scenarios that vary dynamically based on the input image. Since conventional scheduling methods cannot produce schedules for most tasks of this type, a dynamic controller is used to schedule the task and reconfigure the machine “on the fly.” This dynamic scheduling system attempts to balance the overall processing scenario with the needs of the individual routines that make up the task. This paper discusses the implementation of the DISC ( Dynamic Intelligent Scheduling and Control) system. Emphasis is on the scheduling heuristics as they apply to a reconfigurable parallel processor, the information in the system database, and the use of the system for prototyping computer vision/image processing tasks on a partitionable parallel system.

Toward advanced parallel processing: exploiting parallelism at task and instruction levels

The status of two projects that entail the development of a reconfigurable parallel processor system with 128 Sparc microprocessors and a superscalar processor with four operations proceeding in parallel is discussed. The design principles, system configuration, processing element, network architecture, and memory architecture of the reconfigurable processors (called KRPP) are described. The operating system for KRPP is discussed. The architecture for the superscalar (called a dynamically hazard-resolved, statically code-scheduled, nonuniform superscalar) is presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An overview of the Kyushu University reconfigurable parallel processor

As a testbed to investigate systemwide aspects of highly parallel processing, a reconfigurable parallel processor system is currently developed at the Kyushu University in Japan. The system is a MIMD- type multiprocessor which consists of N processing-elements (currently N is 128) fully connected by S N&amp;times;N crossbar networks (currently S is 1). Each processing-element (PE) employs a Fujitsu SPARC MB86900/10 chip-set, a Weitek WTL1164/65 chip-set and 4 Mbytes of memory. Although memory are organized to be distributed among all PEs, the system can be reconfigured as either a memory-shared tightly coupled multiprocessor or a message-passing loosely coupled multiprocessor at run time; also as a hybrid of the two. The crossbar network allows users to take arbitrary topologies for inter-PE (i.e. processor-memory and/or processor-processor) paths under software control of an operating system. The parallel/distributed operating system is also under development to exploit parallelism by making the best of reconfigurability. The full 128-PE configuration will provide up to 1.28 GIPS, 205 MFLOPS (single precision LINPACK), 141 MFLOPS (double precision LINPACK), 512 Mbytes of memory and 1.28 Gbytes/s inter-PE communication. This paper outlines the reconfigurable network and memory architectures among several unique architectural features of the reconfigurable parallel processor.

Determining an Optimal Secondary Storage Service Rate for the PASM Control System

One class of reconfigurable parallel processing systems is based on the use of a large number of processing elements which can be partitioned into multiple virtual machines. Each virtual machine is controlled by one or more control units. The multiple control units in such a system share a common secondary storage for programs. The control units use paging to transfer programs to their primary memories. One design problem is determining the service rate for the secondary storage of the control units, where the optimal is characterized by maximum processor utilization. The PASM parallel processing system is used as a example system to study this problem. The implementation of virtual memory on the PASM control system memory hierarchy is discussed and a queueing network model for the memory hierarchy is developed. Based on assumed values for parameters that characterize the expected task environment, an service rate is derived from the model. The values of the parameters in the model can be varied to determine the impact these changes would have on system performance. Simulation results verifying various aspects of the model are presented and the results are generalized.

Task Preloading Schemes for Reconfigurable Parallel Processing Systems

One class of reconfigurable parallel processing systems is based on the use of a large number of processing elements where each processing element consists of a processor and a primary memory. To efficiently employ the processing elements, it is desirable to overlap the operation of the secondary storage with computations being performed by the processors. Due to the dynamically reconfigurable architecture of such systems, the processors which will execute a new task may not be selected until they are ready to run the task. That is, a task must be preloaded prior to the final selection of the processors on which it will execute. Two schemes which allow for the secondary storage to preload input data and programs into the primary memories so that processor utilization can be increased and system response time decreased are presented. PASM is used as an example system for comparing the performance of the schemes by simulation studies. Results show that both methods are effective techniques. These schemes can be applied to reconfigurable parallel processing systems which use a centralized scheduling policy.

A Reconfigurable Parallel Processor with Microprogram Control

This system's microprogrammable features, implemented through a simple data routing scheme, require only about 18 percent of the total number of processing-element gates.

A reconfigurable parallel processing structure for adaptive state estimation

The computational requirement of adaptive state estimation is examined, and a previously proposed chain parallel processor is extended to satisfy these requirements. An example is programmed in detail to illustrate the flexibility of the structure. During each integration cycle, the processing elements operate in a single-instruction stream mode by accessing a common program, they then re-configure and operate in a multi-instruction stream mode to execute the second part of the algorithm.