Reconfigurable Logic Blocks Research Articles

Design of Reconfigurable Logic Block Based Sequential Circuits Using Look Up Table Logics

Reconfigurable sequential circuits find applications in various digital systems, including communication networks, data processing units, embedded systems, and FPGA-based designs. Their ability to adapt and reconfigure their functionality onthe-fly allows them to accommodate dynamic requirements and optimize the use of hardware resources. Traditional implementations of sequential circuits involve static configurations, where the logic and functionality are fixed during synthesis. While these methods are straightforward to design and implement, they lack adaptability and cannot be modified without redesigning the entire circuit. The proposed method involves the utilization of a dedicated Reconfigurable Logic Block (RLB) within the sequential circuits, allowing for dynamic configuration changes without altering the overall circuit structure. The RLB can be programmed to provide different logic functions using look up tables, multiplexers, enabling the sequential circuit such as counters and shift registers to change its behaviour.

A large-scale comprehensive evaluation of single-slice ring oscillator and PicoPUF bit cells on 28-nm Xilinx FPGAs

Lightweight implementation of security primitives, e.g., physical unclonable functions (PUFs) and true random number generator, in field programmable gate array (FPGA) is crucial replacement of the conventional decryption key stored in battery-backed random access memory or E-Fuses for the protection of field reconfigurable assets. A slice is the smallest reconfigurable logic block in an Xilinx FPGA. The entropy exploitable from each slice of an FPGA is an important factor for the design of security primitives. Previous research has shown that the locations of slices can impact the quality of delay-based PUF designs implemented on FPGAs. To investigate the effect of the placement of each single-bit PUF cell free from the routing resource constraint between slices, single-bit ring oscillator (RO) and identity-based PUF design (Pi-coPUF) cells that can each be fully fitted into a single slice are evaluated. To accurately evaluate their statistical performance, data from a large number of devices are required. To this end, 217 Xilinx Artix-7 FPGAs has been employed to provide a large-scale comprehensive analysis for the two designs. This is the first time single-slice disorder-based security entities have been investigated and compared on 28-nm Xilinx FPGA. Uniqueness, uniformity, correlation, reliability, bit-aliasing and min-entropy of each type of cell are evaluated for four different types of cell placement. Our experimental results corroborate that the location of both cell types in the FPGA affects their performances. For both cell types, the lower the correlation between devices, the higher the min-entropy and uniqueness. Overall, the min-entropy, correlation and uniqueness of PicoPUF are slightly higher than those of RO. Otherwise, the uniformity, bit-aliasing and reliability of the PicoPUF are slightly lower than those of the RO. Comparing the resource usage and metrics of the PicoPUF, ring oscillator PUF and some existing memory-based PUF implementations, PicoPUF stands out as a lightweight FPGA-based weak PUF design. The raw data for the PicoPUF design are made publicly available to enable the research community to use them for benchmarking and/or validation.

Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains

Heterogeneous computing systems with tightly coupled processors and reconfigurable logic blocks provide great scope to improve software performance by executing each section of code on the processor or custom hardware accelerator that best matches its requirements and the system optimisation goals. This article is motivated by the idea of a software tool that can automatically accomplish the task of deploying code, originally written for a conventional computer, to the processors and reconfigurable logic blocks in a heterogeneous system. We undertake an extensive survey of high-level synthesis tools to determine how close we are to this vision, and to identify any capability gaps. The survey is structured according to a new framework that clearly expresses the relationships between the many tools surveyed. We find that none of the existing tools can deploy general high-level code without manual intervention. Logic synthesis from arbitrary high-level code remains an open problem with dynamic data structures, function pointers and recursion all presenting challenges. Other challenges include automating the tasks of code partitioning, optimisation and design space exploration.

Hardware redundancy architecture based on reconfigurable logic blocks with persistent high reliability improvement

On-chip digital system reliability is an important concern today in many critical applications. To achieve high reliability, hardware redundancy architectures are often employed. One of the most frequently used architectures is the triple modular redundancy due to its simplicity and good reliability improvement in the early stages of a product lifetime. However, one of its main drawbacks is the high area overhead, which presents a problem especially in non-time-critical applications. An alternative approach based on reconfigurable logic blocks is proposed in this paper for non-time-critical applications. The aim is to reduce the area overhead below the triple modular redundancy levels while also improving the overall system reliability over the entire operational stage of the product lifetime. Experimental results show that using reconfigurable logic blocks instead of triple modular redundancy the area overhead of redundancy can be significantly reduced up to 71% while also increasing the system reliability over the entire lifetime.

An Integrated Circuit Design for a Dynamics-Based Reconfigurable Logic Block

In this brief, a nonlinear integrated circuit to harvest different types of digital computation from complex dynamics is designed and fabricated. This circuit can be dynamically reconfigured to implement different two-input, one-output digital functions. The main advantage of the circuit is the ability to implement different digital functions in each clock cycle without halting for reconfiguration.

Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration

Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, without compromising on performance. We present a framework that aims to increase the performance benefits of reconfigurable processors that support full or partial runtime reconfiguration. The proposed framework achieves this by: (1) providing a means for choosing suitable custom instruction selection heuristics, (2) leveraging FPGA-aware merging of custom instructions to maximize the reconfigurable logic block utilization in each configuration, and (3) incorporating a hierarchical loop partitioning strategy to reduce runtime reconfiguration overhead. We show that the performance gain can be improved by employing suitable custom instruction selection heuristics that, in turn, depend on the reconfigurable resource constraints and the merging factor (extent to which the selected custom instructions can be merged). The hierarchical loop partitioning strategy leads to an average performance gain of over 31% and 46% for full and partial runtime reconfiguration, respectively. Performance gain can be further increased to over 52% and 70% for full and partial runtime reconfiguration, respectively, by exploiting FPGA-aware merging of custom instructions.

EXPERIMENTAL REALIZATION OF A RECONFIGURABLE THREE INPUT, ONE OUTPUT LOGIC FUNCTION BASED ON A CHAOTIC CIRCUIT

This paper addresses and reports the construction of a reconfigurable logic block that can morph between all three input, one output logic functions based on chaos computing theory. The logic block is constructed based on a discrete chaotic circuit and can emulate all three input, one output logic functions. We have derived instruction set table of this logic block from the block that can be used as a look up table to generate any special three input, one output logic function. Additionally, sensitivity of constructed logic block to noise is investigated and a method for enhancing robustness of block with respect to the environment noise is proposed and implemented. This chaotic block offers inventive approaches for constructing higher order logic functions.

Reconfigurable Logic blocks based on a discrete chaotic circuit: Implementation of all fundamental two input, one output logic functions

In this paper, we implement the first realization of a reconfigurable chaotic based logic block that can morph between all two input, one output logic functions. This logic block is constructed based on a discrete time chaotic circuit known as Logistic Map and can directly emulate operation of all two input, one output combinational functions. We have derived instruction set table of this logic block that can be used as a look up table to generate different logic functions. Furthermore, we propose a method to enhance robustness of the constructed logic block with respect to environmental noise. Constructed logic block provides opportunities and possibilities to construct more efficient and higher order reconfigurable logic blocks.

A Novel dynamically reconfigurable logic block based on CHAOS

Abstract The new idea of chaos based computation is studied and improved to obtain a novel logic block. In new presented scheme rcconfigurability is produced through intrinsic flexibility of chaotic systems. Handle for directing the logic block to simulate different kinds of digital functions is the offsets that one gives to the data inputs. A new form of dynamic reconfiguration that is beyond the conventional meaning of dynamic reconfiguration in FPGAs is introduced. Introduced scheme could reconfigure itself by the arrival of new set of data and control inputs and no suspension in the operation of the system is needed.