Hardware redundancy architecture based on reconfigurable logic blocks with persistent high reliability improvement

Abstract

On-chip digital system reliability is an important concern today in many critical applications. To achieve high reliability, hardware redundancy architectures are often employed. One of the most frequently used architectures is the triple modular redundancy due to its simplicity and good reliability improvement in the early stages of a product lifetime. However, one of its main drawbacks is the high area overhead, which presents a problem especially in non-time-critical applications. An alternative approach based on reconfigurable logic blocks is proposed in this paper for non-time-critical applications. The aim is to reduce the area overhead below the triple modular redundancy levels while also improving the overall system reliability over the entire operational stage of the product lifetime. Experimental results show that using reconfigurable logic blocks instead of triple modular redundancy the area overhead of redundancy can be significantly reduced up to 71% while also increasing the system reliability over the entire lifetime.