Reconfigurable Interconnection Research Articles

A Versatile 3D-Printable Soft Pneumatic Actuator Design for Multi-Functional Applications in Soft Robotics.

Soft pneumatic actuators (SPAs) play a crucial role in generating movements and forces in soft robotic systems. However, existing SPA designs require significant structural modifications to be used in applications other than their original design. The present article proposes an omni-purpose fully 3D-printable SPA design inspired by membrane type mold and cast SPAs. The design features a spring-like zig-zag structure 3D-printed using an affordable 3D printer with thermoplastic polyurethane and a minimum wall thickness between 0.4 and 0.6 mm. The new SPA can perform unidirectional extension (30% extension) and bidirectional (rotation around same axis) bending (100°), with the ability to exert 10 N blocking force for 350 kPa pressure input. In addition, the design exhibits the capability to be scaled down for the purpose of accommodating limited spaces, while simultaneously enabling the reconfigurable interconnection of multiple SPAs to adapt to larger areas and navigate intricate trajectories that were not originally intended. The SPA's ability to be used in multiple applications without structural modification was validated through testing as a robot end-effector (gripper), artificial muscles in a soft tendon-driven prosthetic hand, a tube/tunnel navigator, and a robot crawler.

Improving Utilization of Dataflow Unit for Multi-Batch Processing

Dataflow architectures can achieve much better performance and higher efficiency than general-purpose core, approaching the performance of a specialized design while retaining programmability. However, advanced application scenarios place higher demands on the hardware in terms of cross-domain and multi-batch processing. In this article, we propose a unified scale-vector architecture that can work in multiple modes and adapt to diverse algorithms and requirements efficiently. First, a novel reconfigurable interconnection structure is proposed, which can organize execution units into different cluster typologies as a way to accommodate different data-level parallelism. Second, we decouple threads within each DFG node into consecutive pipeline stages and provide architectural support. By time-multiplexing during these stages, dataflow hardware can achieve much higher utilization and performance. In addition, the task-based program model can also exploit multi-level parallelism and deploy applications efficiently. Evaluated in a wide range of benchmarks, including digital signal processing algorithms, CNNs, and scientific computing algorithms, our design attains up to 11.95× energy efficiency (performance-per-watt) improvement over GPU (V100), and 2.01× energy efficiency improvement over state-of-the-art dataflow architectures.

Hardware Trojan Attacks on the Reconfigurable Interconnections of Field-Programmable Gate Array-Based Convolutional Neural Network Accelerators and a Physically Unclonable Function-Based Countermeasure Detection Technique.

Convolutional neural networks (CNNs) have demonstrated significant superiority in modern artificial intelligence (AI) applications. To accelerate the inference process of CNNs, reconfigurable CNN accelerators that support diverse networks are widely employed for AI systems. Given the ubiquitous deployment of these AI systems, there is a growing concern regarding the security of CNN accelerators and the potential attacks they may face, including hardware Trojans. This paper proposes a hardware Trojan designed to attack a crucial component of FPGA-based CNN accelerators: the reconfigurable interconnection network. Specifically, the hardware Trojan alters the data paths during activation, resulting in incorrect connections in the arithmetic circuit and consequently causing erroneous convolutional computations. To address this issue, the paper introduces a novel detection technique based on physically unclonable functions (PUFs) to safeguard the reconfigurable interconnection network against hardware Trojan attacks. Experimental results demonstrate that by incorporating a mere 0.27% hardware overhead to the accelerator, the proposed hardware Trojan can degrade the inference accuracy of popular neural network architectures, including LeNet, AlexNet, and VGG, by a significant range of 8.93% to 86.20%. The implemented arbiter-PUF circuit on a Xilinx Zynq XC7Z100 platform successfully detects the presence and location of hardware Trojans in a reconfigurable interconnection network. This research highlights the vulnerability of reconfigurable CNN accelerators to hardware Trojan attacks and proposes a promising detection technique to mitigate potential security risks. The findings underscore the importance of addressing hardware security concerns in the design and deployment of AI systems utilizing FPGA-based CNN accelerators.

Advances in Multi‐Terminal Transistors as Reconfigurable Interconnections for Neuromorphic Sensing and Processing

AbstractInspired by the brain, neuromorphic computing seeks to improve data‐centric applications in terms of power consumption and device footprint. The processing efficiency can be attributed to reconfigurable connections coupled with complex dynamics and efficient data sensing and signal processing. With field‐effect tunability, the three‐terminal thin‐film transistor is initially explored as a switch. Recently, transistors with added gates and modes have been fashioned as multi‐terminal devices capable of interconnecting complex networks and transducing multiple inputs. Here, the advances in both the semiconducting channel material and the configurational design of multi‐terminal devices are reviewed. The use of strong coupling and dynamical material properties in novel ion‐based capacitors, mixed‐ionic‐electronic semiconductors, low‐dimensional confined systems, stimuli‐responsive materials and redox‐active semiconductors has enabled new neuromorphic functionalities. These include improving reconfigurability using the regulatory ability of homeostasis, dendritic integration of sensory signals and the synaptic competition of resources. The transistor devices are also highly relevant in circuits that improve the efficiency of sensory transduction and signal processing; stimuli‐responsive semiconductors that adapt to the sensory inputs can be employed in the transistors and highly efficient sensorimotor connections between sensors and actuators can be emulated. These highly efficient, low‐complexity analog devices are crucial design elements for next‐generation neuromorphic systems.

Magnetic Liquid Metals: A Review

AbstractMagnetic liquid metal (MLM) is a mixture of magnetic particles with gallium‐based liquid metals which utilizes an unconventional combination of fluidity, high thermal/electrical conductivity, biocompatibility, and magnetism. Recently, from materials to applications, studies on MLMs have drastically increased. Single or multiple MLMs can be precisely positioned or can act as a carrier for handling other objects. MLMs are also used in biomedical applications such as cancer treatment by hyperthermia and precision delivery of cancer drugs on tumors, or antibacterial coating which kills bacteria. In electronics applications, MLMs are used for magnetic field‐driven patterning of metallic lines, reconfigurable interconnects, electronic tattoos, and reconfigurable electromagnetic wave shielding. Phase change (solid/liquid) of MLMs adds another unique capability, morphing. A combination of innovations in the micro/nano robots and MLMs has huge potential to bring an unprecedented disruptive technology for a wide variety of applications including self‐morphing shape‐recovery robots, highly localized cancer treatment, and reconfigurable stealth/camouflage, among others. This article comprehensively reviews recent developments in MLMs from the materials to methods of preparation, locomotion of MLMs, their applications, and future outlooks.

Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays

The architecture of a coarse-grained reconfigurable array (CGRA) interconnect has a significant effect on not only the flexibility of the resulting accelerator, but also its power, performance, and area. Design decisions that have complex trade-offs need to be explored to maintain efficiency and performance across a variety of evolving applications. This paper presents Canal, a Python-embedded domain-specific language (eDSL) and compiler for specifying and generating reconfigurable interconnects for CGRAs. Canal uses a graph-based intermediate representation (IR) that allows for easy hardware generation and tight integration with place and route tools. We evaluate Canal by constructing both a fully static interconnect and a hybrid interconnect with ready-valid signaling, and by conducting design space exploration of the interconnect architecture by modifying the switch box topology, the number of routing tracks, and the interconnect tile connections. Through the use of a graph-based IR for CGRA interconnects, the eDSL, and the interconnect generation system, Canal enables fast design space exploration and creation of CGRA interconnects.

Non-Volatile Nano-Electro-Mechanical Switches and Hybrid Circuits in a 16 nm CMOS Back-End-of-Line Process

Reprogrammable non-volatile (NV) vertically-oriented nano-electro-mechanical (NEM) switches with a compact footprint are successfully implemented using multiple back-end-of-line (BEOL) interconnect layers of a standard 16-nm CMOS process technology, with no additional lithography steps. A compact decoder circuit comprising an array of these reconfigurable interconnects is successfully demonstrated. As the minimum metal pitch decreases with each new manufacturing process generation, hybrid CMOS+NEM technology becomes increasingly attractive for ultra-low-power reconfigurable computing applications.

Dynamic Rate Neural Acceleration Using Multiprocessing Mode Support

Multiobject detection has become an integral component in various neural applications, such as autonomous driving and augmented reality. The system should be able to recognize and process multiple objects simultaneously. Moreover, the performance requirements for this system can be dynamically changed depending on the number of regions of interest (ROIs) in each frame. Consequently, the processing unit (PU) of the neural acceleration system should provide various inference rates. Therefore, we present a field-programmable gate array (FPGA)-based dynamic rate neural acceleration system called MultiLockOn to dynamically change the inference performance according to the number of ROIs per frame. It supports multiprocessing modes with different speeds through the introduction of novel multi-mode processing engines (PEs) comprising minimum reconfigurable interconnections across inference modes to minimize hardware overhead. The MultiLockOn system can provide an improvement of up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> in the inference performance compared to that of DNNWeaver and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.7\times $ </tex-math></inline-formula> compared to that of the ARM Cortex-A53 with minimum accuracy loss by supporting the multiprocessing modes.

A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect

Compute-in-memory (CIM) paradigm using ferroelectric field effect transistor (FeFET) as the weight element is projected to exhibit excellent energy efficiency for accelerating deep neural network (DNN) inference. However, two challenges exist. On the technology level, the chip area scaling is stalled due to the lack of logic voltage compatible FeFET at leading-edge technology node, e. g. 7nm. On the system level, CIM-based inference engine designs are usually customized for a specific DNN model, lacking the flexibility to support different DNN models. Besides, communication latency varies across different DNN models and can bound the total inference latency. Therefore, a reconfigurable interconnect is desired to be adaptive to different workloads, which can induce high area cost due to the reconfigurable circuit modules. To solve these issues, in this work, a system-technology co-design (STCO) of a monolithic 3D (M3D) reconfigurable CIM accelerator is performed, where back-end-of-line (BEOL) compatible oxide channel MOSFET and FeFET technologies are utilized. On the technology level, W-doped indium oxide (IWO) NMOS is utilized to design area-efficient M3D write circuit. On the system level, a reconfigurable interconnect design that inserts workload-specific express link is proposed, where the IWO-based NMOS and FeFET are adopted as the building element of the mux and crossbar switch in the router. The algorithm for interconnect configuration is also devised to achieve optimal latency for different workloads. From the system-level evaluation results, M3D IWO FeFET design (utilizing a hybrid 22nm/7nm M3D partition) shows <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.1\times $ </tex-math></inline-formula> times higher energy efficiency than a 7nm 2D SRAM design with comparable chip area. With the proposed reconfigurable interconnect scheme, the interconnect latency is reduced by 9%~32% compared to the baseline with a regular mesh network.

Silicon Photonic Flex-LIONS for Reconfigurable Multi-GPU Systems

The rapid increases in data-intensive applications demand for more powerful parallel computing systems capable of parallel processing a large amount of data more efficiently and effectively. While GPU-based systems are commonly used in such parallel processing, the exponentially rising data volume can easily saturate the capacity of the largest possible GPU processor. One possible solution is to exploit multi-GPU systems. In a multi-GPU system, the main bottleneck is the interconnect, which is currently based on PCIe or NVLink technologies. In this study, we propose to optically interconnect multiple GPUs using Flex-LIONS, an optical all-to-all reconfigurable interconnect. By exploiting the multiple free spectral ranges (FSRs) of Flex-LIONS, it is possible to adapt (or steer) the inter-GPU connectivity to the traffic demands by reconfiguring the optical connectivity of one FSR while maintaining fixed all-to-all connectivity of another FSR. Simulation results show the benefits of the proposed reconfigurable bandwidth-steering interconnect solution under various traffic patterns of different applications. Execution time reductions by up to 5× have been demonstrated in this study including two applications of convolution and maxpooling.

Deep learning accelerators: a case study with MAESTRO

In recent years, deep learning has become one of the most important topics in computer sciences. Deep learning is a growing trend in the edge of technology and its applications are now seen in many aspects of our life such as object detection, speech recognition, natural language processing, etc. Currently, almost all major sciences and technologies are benefiting from the advantages of deep learning such as high accuracy, speed and flexibility. Therefore, any efforts in improving performance of related techniques is valuable. Deep learning accelerators are considered as hardware architecture, which are designed and optimized for increasing speed, efficiency and accuracy of computers that are running deep learning algorithms. In this paper, after reviewing some backgrounds on deep learning, a well-known accelerator architecture named MAERI (Multiply-Accumulate Engine with Reconfigurable interconnects) is investigated. Performance of a deep learning task is measured and compared in two different data flow strategies: NLR (No Local Reuse) and NVDLA (NVIDIA Deep Learning Accelerator), using an open source tool called MAESTRO (Modeling Accelerator Efficiency via Spatio-Temporal Resource Occupancy). Measured performance indicators of novel optimized architecture, NVDLA shows higher L1 and L2 computation reuse, and lower total runtime (cycles) in comparison to the other one.

Dual-Mode Stable Performance Phase-Shifted Full-Bridge Converter for Wide-Input and Medium-Power Applications

Power converters with an extended range of line voltage are the main requirement in today's industrial applications such as photovoltaics- and supercapacitors-based energy systems. The variation in the line voltage severely degrades the performance of power converters, because of the extended freewheeling interval, more circulation current, narrow range of zero voltage switching, and increased EMI. This article suggests a modified phase-shifted full-bridge converter that cuts the freewheeling interval and minimizes these problems. It extends the input voltage range by keeping the operational duty cycle of the converter high over the wide range of input voltage while maintaining the performance stable. The proposed converter consists of four low-profile transformers having reconfigurable interconnection structure. There are two distinct reconfigurable modes, a series mode and a parallel mode, which can be configured with changes in the operational conditions. The operation of the proposed converter with high switching frequency improves the power density. Additionally, the use of multiple transformers minimizes the heat management efforts and reduces the overall volume of the converter. The proposed work, in this article, is validated in hardware characterization for a wide range of input voltage 100-400 Vdc and up to the load power of 1 kW. The measured energy efficiency of the proposed converter remains stable over the complete range input voltage 100-400 Vdc.

Back-End-of-Line Nano-Electro-Mechanical Switches for Reconfigurable Interconnects

Non-volatile (NV) nano-electro-mechanical (NEM) switches are successfully implemented using multiple metallic layers in a standard 65 nm CMOS back-end-of-line (BEOL) process with no additional lithography steps. Non-volatile operation of a NEM switch as a reconfigurable interconnect to dynamically change CMOS circuit functionality is demonstrated.

Achieving Flexible Global Reconfiguration in NoCs Using Reconfigurable Rings

The communication behaviors in NoCs of chip-multiprocessors exhibit great spatial and temporal variations, which introduce significant challenges for the reconfiguration in NoCs. Existing reconfigurable NoCs are still far from ideal reconfiguration scenarios, in which globally reconfigurable interconnects can be immediately reconfigured to provide bandwidths on demand for varying traffic flows. In this paper, we propose a hybrid NoC architecture that globally reconfigures the ring-based interconnect to adapt to the varying traffic flows with a high flexibility. The ring-based interconnect has the following advantages. First, it includes horizontal rings and vertical rings, which can be dynamically combined or split to provide low-latency channels for heavy traffic flows. Second, each combined ring connects a number of nodes, thereby improving both the utilization of each ring and the probability to reuse previous reconfigurable interconnects. Finally, the reconfiguration algorithm has a linear-time complexity and can be implemented using a low-overhead hardware design, making it possible to achieve a fast reconfiguration in NoCs. The experimental results show that compared to recent reconfigurable NoCs, the proposed NoC architecture can greatly improve the saturation throughput for synthetic traffic patterns, and reduce the packet latency over 40 percent for realistic benchmarks without incurring significant area and power overhead.

A Modified Higher Operational Duty Phase Shifted Full Bridge Converter for Reduced Circulation Current

Besides many advantages, the reduction in the operational duty of a traditional phase shifted full converter limits its scope in applications where a wide range of input voltage is the main requirement. Operation with low duty cycle extends freewheeling interval, which results in degraded performance such as more circulating current, increased conduction loss in power devices, narrow range of zero voltage switching and increased EMI. To overcome these drawbacks, this work suggests a modified phase shifted full bridge converter that keeps the operational duty of the converter high for a wide range of input voltage. This cuts the freewheeling interval and improves performance. The proposed converter consists of four low profile transformers having a structure of reconfigurable interconnections. There are two distinct reconfigurable operational modes, a low-gain mode and a high-gain mode, which can be adopted following the variation in line voltage. The proposed work is validated in LTspice simulation and hardware characterization for a wide range of input voltage 100-400 Vdc/ 12 Vout and up to the load power of 1.2 kW.

Short-range optical wireless communications for indoor and interconnects applications

Optical wireless communications have been widely studied during the past decade in short⁃range applications, such as indoor high⁃ speed wireless networks and interconnects in data centers and high⁃performance computing. In this paper, recent developments in high⁃speed short⁃range optical wireless communications are reviewed, including visible light communications (VLCs), infrared in-door communication systems, and reconfigurable optical interconnects. The general architecture of indoor high⁃speed optical wire⁃ less communications is described, and the advantages and limitations of both visible and infrared based solutions are discussed. The concept of reconfigurable optical interconnects is presented, and key results are summarized. In addition, the challenges and potential future directions of short⁃range optical wireless communications are discussed.

Analysis of Dissipative Losses in Modular Reconfigurable Energy Storage Systems Using SystemC TLM and SystemC-AMS

Battery storage systems are becoming more popular in the automotive industry as well as in stationary applications. To fulfill the requirements in terms of power and energy, the literature is increasingly discussing electrically reconfigurable interconnection topologies. However, these topologies use switching elements on the cell and module level that exhibit an electric resistance due to their design and hence generate undesirable dissipative losses. In this article, we propose a new analysis and optimization framework to examine and minimize the losses in such topologies. For this purpose, we develop a SystemC model to investigate static and dynamic load scenarios, e.g., from the automotive domain. The model uses SystemC TLM for the digital subsystem, SystemC-AMS for the mixed-signal subsystem, and host-compiled simulation for the microcontroller executing the embedded software. Here, we analyze the impact of the dissipative losses on the system efficiency that depend on the modularization level, implying the number of serial and parallel switching elements. Our analysis clearly shows that in reconfigurable topologies, the modularization level has a significant influence on the losses, which in our automotive example covers several orders of magnitude. For the topologies we have investigated, the highest efficiency can be reached when a parallel-only modularization is aspired and the number of serial switching elements is minimized. It is also shown that the losses of the state-of-the-art topology with one battery pack protection switch are almost as high as in a smart cell approach in which each energy storage cell has its own switching element. However, due to the high number of switching elements, this results in a reduction of energy density and increases the system costs, showing that this is a multi-criteria optimization problem.

A Wide Load Current and Voltage Range Switched Capacitor DC–DC Converter with Load Dependent Configurability for Dynamic Voltage Implementation in Miniature Sensors

Advancements in low power circuits and batteries have enabled the design of miniature sensors with tiny batteries. In such systems, implementing dynamic voltage scaling (DVS) is crucial for maximizing system lifetime. In this paper, a new switched capacitor (SC) converter that is capable of handling a wide range of load currents and output voltages is presented for on-chip DVS implementation. The proposed converter consists of multi-ratio multi-leaf SC stages and reconfigurable interconnect, enabling fine voltage resolution. The stage interconnect scheme enables cascaded or parallel connection of stages. The multi-leaf structure allows load-dependent switch size selection, offering a better trade-off between losses over a wide load range. A limited-voltage-swing switch-driving scheme allows efficient down-conversion from high battery voltage input. A prototype was fabricated in a 180 nm process, providing an output voltage with effective resolution of 16 mV over a load current range of 300 nA to 300 μA (1000×) from a 4 V battery. Efficiency greater than 62% and a peak efficiency of 77% are achieved under a light load (500 nA) over a voltage range of 400 mV to 1.6 V. Efficiency greater than 64% and a peak efficiency of 72% are achieved under a heavy load (200 μA) over a voltage range of 700 mV to 1.6 V.

Free Space Intra-Datacenter Interconnects Based on 2D Optical Beam Steering Enabled by Photonic Integrated Circuits

Data centers are continuously growing in scale and can contain more than one million servers spreading across thousands of racks; requiring a large-scale switching network to provide broadband and reconfigurable interconnections of low latency. Traditional data center network architectures, through the use of electrical packet switches in a multi-tier topology, has fundamental weaknesses such as oversubscription and cabling complexity. Wireless intra-data center interconnection solutions have been proposed to deal with the cabling problem and can simultaneously address the over-provisioning problem by offering efficient topology re-configurability. In this work we introduce a novel free space optical interconnect solution for intra-data center networks that utilizes 2D optical beam steering for the transmitter, and high bandwidth wide-area photodiode arrays for the receiver. This new breed of free space optical interconnects can be developed on a photonic integrated circuit; offering ns switching at sub-μW consumption. The proposed interconnects together with a networking architecture that is suitable for utilizing those devices could support next generation intra-data center networks, fulfilling the requirements of seamless operation, high connectivity, and agility in terms of the reconfiguration time.

Controlling On-chip Optical Radiation with All-Dielectric Antennas: Reconfigurable Interconnects and Lab-on-achip Devices

Aimed to improve the flexibility of optical network-on-a-chip topologies, unguided optical interconnects using plasmonic nanoantennas or dielectric phased arrays have been proposed. However, the bulky footprints of the latter, and both the low directivity figures and high losses of the former, together with complicated excitation schemes, limit their use for on-chip optical interconnects. Here, we introduce a novel concept of on-chip CMOS-compatible wireless optical system based on the use of smartly-engineered broadband easily-fed antennas, which not only overcomes the aforementioned drawbacks but also opens a wide range of applications in several fields. To illustrate its potential, several unprecedented on-chip wireless applications are outlined and experimentally demonstrated. This includes the verification of broadband highly-directive wireless data transmission at speeds as high as 160 Gbit·s−1 over mm-scale links, the realization of fully-reconfigurable wireless beam steering device and the validation of an ultra-compact integrated contactless microflow cytometer.