Reconfigurable Hardware Research Articles

Reconfigurable data intensive service for low latency cyber-physical systems and IoT communication

<span>The fourth industrial revolution is realized through the many developments in cyber-physical systems (CPS) made possible by the widespread use of the internet of things (IoT). CPS sensor networks must enable mobile and wireless CPSs with their specific flexibility and heterogeneity needs without compromising quality of service (QoS). The research article focuses on reconfigurable data communication hardware for numerous IoT-supporting infrastructures and performance estimation using delay, power, throughput, and packet delivery ratio (PDR) for different IoT node configurations. Tree topology-based network configuration from cloud data to sensor fog organizers, sensor network directors, and IoT-embedded sensors is supported. Functional simulation is performed in iFoGSim, Xilinx ISE, and Modelsim 10.0 with a maximum of 64 variable nodes programmed for data communication and interplay verification with a minimum delay of 9.1 ns, maximum frequency of 319 MHz, power of 7.5 mW, throughput of 0.280, and maximum PDR=1. The simulation is applicable for fog computing and CPS processed from different alters in specific topologies.</span>

Hardware Design Strategies Oriented to Edge Computing and AgriFood Electronics for Image Processing using Cellular Automata

There has been a growing interest from academia and industry in developing circuits and systems for edge computing and quality control tasks in food production lines, where image-processing is frequently required. This paper outlines the required considerations for designing a fruit classification system based on image-processing using Cellular Automata (CA) models and integrating it into reconfigurable hardware (HW) such as Field Programmable Gate Arrays (FPGAs). Parallel processing in CA requires numerous processing elements to be implemented and mapping CA models to HW generally comes with limitations. Homogeneous CA arrays are easier to design and implement in HW but can be resource-demanding. To fill this gap, this study explores different alternatives for the HW implementation of CA models, particularly trading computational-parallelism for a more optimized use of the available HW resources. We conducted experimental tests of the designed HW system using the Digilent Nexys development board, and the operation was validated against software-based benchmarks for image-processing, particularly concerning edge-detection. The presented study provides a broader range of design solutions for the HW implementation of two-dimensional CA models and a better understanding of their advantages and disadvantages. The results show that solutions focusing on instruction-parallelism add some complexity to the conception and require more design effort, compared to homogeneous CA models composed of identical cells. However, the instruction-parallel design solutions can significantly improve the HW resource utilization, especially when implementing computationally intensive CA rules in FPGAs.

A Survey On Image Registration Techniques Using FFT

Image Registration is the process of straightening two or more images of the same scene with testimonial to a particular image. The images are captured from various sensors at different times and at multiple viewpoints. Thus, to get a better picture of any change of a scene/object over a considerable period of time image registration is important. Image registration finds application in medical sciences, remote sensing and in computer vision. This paper presents a detailed review of several approaches which are classified accordingly along with their contributions and drawbacks. The main steps of an image registration procedure are also discussed. Different performance measures are presented that determine the registration quality and accuracy. The scope for the future research are presented as well. Applications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power, plus the ability to experiment with algorithms. Reconfigurable hardware devices in the form of Field Programmable Gate Arrays (FPGAs) have been proposed as a way of obtaining high performance at an economical price. At present, however, users must program FPGAs at a very low level and have a detailed knowledge of the architecture of the device being used. To try to reconcile the dual requirements of high performance and ease of development, this paper reports on the design and realization of a High-Level framework for the implementation of 1-D and 2-D FFTs for real-time applications. Results show that the parallel implementation of 2-D FFT achieves virtually linear speed-up and real-time performance for large matrix sizes. Finally, an FPGA-based parametrizable environment based on the developed parallel 2-D FFT architecture is presented as a solution for frequency domain image filtering application

FPGA-Based Numerical Simulation of the Chaotic Synchronization of Chua Circuits

The objective of this work was to design and implement a system based on reconfigurable hardware as a study tool for the synchronization of chaotic circuits. Mathematical models were established for one circuit, two synchronized, and multiple synchronized Chua circuits. An ordinary differential equation solver was developed applying Euler’s method using the Verilog hardware description language and synthesized on a Spartan 3E FPGA (Field-Programmable Gate Array) equipped with a 32-bit RISC processor, 64 MB of DDR SDRAM, and 4 Mb of PROM. With a step size of 0.005 and a total of 10,000 iterations, the state equations for one and three Chua circuits were solved at a time of 0.2 ms and a frequency of 50 Mhz. The logical resources used by the system did not exceed 4%. To verify the operation, a numerical simulation was carried out using the Octave V9.1.0 calculation software on an Intel(R) Core i7-9750H CPU 2.59 GHz computer, obtaining the same results but in a time of 493 ms and 3.177 s for one and three circuits, respectively.

Implementation of Dimension Order Routing Algorithm on Reconfigurable Hardware for NoC applications

Inter-processing element communication encounters significant hurdles arising from constraints in power consumption, physical space, and data transfer speed. Storing data packets temporarily during communication uses a lot of the chip's power. Many contemporary network-on-chip (NoC) architectures are heavily resource-intensive due to the extensive use of router buffers. Eliminating these buffers and virtual channels can streamline router design and reduce power consumption. The routing and arbitration strategies implemented within a NoC router are pivotal for optimizing the overall performance of the NoC mesh. The routing algorithm plays a critical role in NoC systems, as it is responsible for balancing traffic load across network channels, even in scenarios of asymmetric traffic distribution. This paper introduces a model for X-Y routing algorithms, specifically tailored for implementation on FPGA platforms utilizing a flexible state diagram. The distinctive contribution of this research lies in its synthesis and optimized realization of the X-Y routing algorithm on FPGAs, providing Network-on-Chip (NoC) designers with a robust framework for developing efficient routers tailored to their FPGA architectures.

An efficient controller-based architecture for AES algorithm using FPGA

An efficient controller-based architecture for AES algorithm using FPGA

NC-Library: Expanding SystemC Capabilities for Nested reConfigurable Hardware Modelling

As runtime reconfiguration is used in an increasing number of hardware architectures, new simulation and modeling tools are needed to support the developer during the design phases. In this article, a language extension for SystemC is presented, together with a design methodology for the description and simulation of dynamically reconfigurable hardware at different levels of abstraction. The library presented offers a high degree of flexibility in the description of reconfiguration features and their management, while allowing runtime reconfiguration simulation, removal, and replacement of custom modules as well as third-party components throughout the architecture development process. In addition, our approach supports the emerging concept of nested reconfiguration and split regions with a minimal simulation overhead of a maximum of three delta cycles for signal and transaction forwarding, and four delta cycles for the reconfiguration process.

A Survey of Computationally Efficient Graph Neural Networks for Reconfigurable Systems

Graph neural networks (GNNs) are powerful models capable of managing intricate connections in non-Euclidean data, such as social networks, physical systems, chemical structures, and communication networks. Despite their effectiveness, the large-scale and complex nature of graph data demand substantial computational resources and high performance during both training and inference stages, presenting significant challenges, particularly in the context of embedded systems. Recent studies on GNNs have investigated both software and hardware solutions to enhance computational efficiency. Earlier studies on deep neural networks (DNNs) have indicated that methods like reconfigurable hardware and quantization are beneficial in addressing these issues. Unlike DNN research, studies on efficient computational methods for GNNs are less developed and require more exploration. This survey reviews the latest developments in quantization and FPGA-based acceleration for GNNs, showcasing the capabilities of reconfigurable systems (often FPGAs) to offer customized solutions in environments marked by significant sparsity and the necessity for dynamic load management. It also emphasizes the role of quantization in reducing both computational and memory demands through the use of fixed-point arithmetic and streamlined vector formats. This paper concentrates on low-power, resource-limited devices over general hardware accelerators and reviews research applicable to embedded systems. Additionally, it provides a detailed discussion of potential research gaps, foundational knowledge, obstacles, and prospective future directions.

A Reconfigurable Hardware Realization for Real-Time Simulation of Cardiac Excitation and Conduction

Dynamic simulation of complex cardiac excitation and conduction requires high computational time. Thus, the hardware techniques that can run in real-time simulation were introduced. However, according to existing studies, the hardware simulation requires high power consumption and involves a large size of the physical parts. Due to the drawbacks, this research presents the adaptation of nonlinear Ordinary Differential Equation (ODE)-based cardiac excitable models of Luo-Rudy Phase I (LR-I) and FitzHugh-Nagumo (FHN) in a reconfigurable hardware of field-programmable gate array (FPGA). FPGA rapid prototyping using MATLAB Hardware Description Language (HDL) Coder was used to convert a fixed-point MATLAB Simulink blocks design of the cardiac models into a synthesizable VHSIC Hardware Description Language (VHDL) code and verified using the FPGA-In-the Loop (FIL) Co-simulator. The Xilinx FPGA Virtex-6 XC6VLX240T ML605 evaluation board was chosen as the FPGA platform. The cardiac excitation response characteristics using the LR-I model and the simulations of reentrant initiation and annihilation using the FHN model were verified in Virtex-6 FPGA. This means a new real-time simulation-based analysis technique of cardiac electrical excitation and conduction wassuccessfully developed using the reconfigurable hardware.

Voltage Scaled Low Power DNN Accelerator Design on Reconfigurable Platform

The exponential emergence of Field-Programmable Gate Arrays (FPGAs) has accelerated research on hardware implementation of Deep Neural Networks (DNNs). Among all DNN processors, domain-specific architectures such as Google’s Tensor Processor Unit (TPU) have outperformed conventional GPUs (Graphics Processing Units) and CPUs (Central Processing Units). However, implementing low-power TPUs in reconfigurable hardware remains a challenge in this field. Voltage scaling, a popular approach for energy savings, can be challenging in FPGAs, as it may lead to timing failures if not implemented appropriately. This work presents an ultra-low-power FPGA implementation of a TPU for edge applications. We divide the systolic array of a TPU into different FPGA partitions based on the minimum slack value of different design paths of Multiplier Accumulators (MACs). Each partition uses different near-threshold (NTC) biasing voltages to run its FPGA cores. The biasing voltage for each partition is roughly calculated by the proposed static schemes. However, further calibration of biasing voltage is performed by the proposed runtime scheme. To overcome the timing failure caused by NTC, the MACs with higher minimum slack are placed in lower-voltage partitions, while the MACs with lower minimum slack paths are placed in higher-voltage partitions. The proposed architecture is implemented in a commercial platform, namely Vivado with Xilinx Artix-7 FPGA and academic platform VTR with 22 nm, 45 nm and 130 nm FPGAs. Any timing error caused by NTC can be caught by the Razor flipflop used in each MAC. The proposed voltage-scaled, partitioned systolic array can save 3.1% to 11.6% of dynamic power in Vivado and VTR tools, respectively, depending on the FPGA technology, partition size, number of partitions and biasing voltages. The normalized performance and accuracy of benchmark models running on our low-power TPU are very competitive compared to existing literature.

Boosting general-purpose stream processing with reconfigurable hardware

Reconfigurable devices such as field-programmable gate arrays (FPGAs) offer flexible solutions to workload acceleration with high energy efficiency. Despite such a potential advantage, they often reveal hard to program by application programmers. High-level synthesis languages have been developed to provide higher-level abstractions, allowing the developers to define the FPGA behavior using an imperative programming approach based on C/C++ languages. However, such approaches still leave the developer with the responsibility to harness the low-level optimizations required to develop efficient FPGA programs. Along this line, this paper introduces FSPX, a framework helping programmers to develop FPGA-accelerated data stream processing (DSP) applications. The approach provides a high-level Python API to develop the data-flow graph of operators, which is automatically translated into an efficient Vitis source code targeting Xilinx devices. The execution of the bitstreams implementing two benchmark applications showcases the efficiency of using FPGAs for DSP workloads. In general, FSPX provides, with a reasonable time-to-solution, higher performance compared with state-of-the-art DSP frameworks.

Security Enabled New Term Weight Measure Technique with Data Driven for Next Generation Mobile Computing Networks

In the field of ASIC and FPGA, Machine Learning (ML) techniques play a major role and become predominant for accurate results for different applications like big data analysis and automotive electronics, and driverless vehicles which are required speed and power savings. Due to increasing the demand for higher accuracy, low power, low area consumption, and higher throughput for the complexity of the designs in the latest technology, the proposed system is fulfilling these demands in ASIC and FPGA domains, reconfigurable hardware architecture has been proposed it consists of an ML-based Support Vector Machine (SVM), high-speed AHB protocol and Floating point (FP) operations and also the system has the flexibility to communicate with I2C and I2S protocols. In order to increase throughput with minimal latency, the proposed architecture with AHB protocol and AHB to APB bridge is incorporated between the fabric dynamically reconfigurable multi-processor (FDPM) and peripherals along with security algorithms using SHA-256bits and AES. In order to perform ML-based applications, the proposed system is incorporated double-precision floating point (DPFP) arithmetic operations. The overall proposed architecture is developed in Verilog HDL and quality checking using the LINT tool and Clock Domain Crossing (CDC) using Spyglass tool and synthesized using DC compiler for ASIC and Vivado Design Suite 2018.1 for FPGA implementation and verification. The entire design is interfaced with the Zynq processor and SDK tool to verify data transfer between hardware and software. The obtained results show the generated custom accelerator is able to compute any complex ML classifiers for a larger amount of data. The obtained results are compared with existing state-of-art results and found that 18 % improvement in throughput, a 21 % improvement in power consumption savings, and a 34 % reduction in latency.

Reconfigurable open architecture control system with integrated digital twin for 3-axis woodworking milling machine

ABSTRACT This study proposes a reconfigurable open architecture control system for the Computer Numerical Control (CNC) woodworking educational machine tool called “EMCO F1 CNC”. On this machine physical hardware reconfiguration (spindle position can be vertical and horizontal) is possible. The idea was to develop a control system that would follow the configuration changes of the machine tool. The educational character of the machine and its reconfigurability demand possibilities for machining programme simulations in order to determine optimal workpiece position in the workspace and programme verification. Those are the reasons for developing a virtual machine tool integrated with the control system as a digital twin. The study presents a novel methodology for the development of control systems, merging the concept of “virtual commissioning” with iterative error-driven processes. The objective was to develop a dynamic control system capable of promptly adjusting to kinematics changes in real time. In a wood machining experiment, a test workpiece for machine tools for both machine configurations verified the operation of the developed control system.

Reconfigurable Signal Processing and DSP Hardware Generator for 5G and Beyond Transmitters

Reconfigurable Signal Processing and DSP Hardware Generator for 5G and Beyond Transmitters

S2RNN: Self-Supervised Reconfigurable Neural Network Hardware Accelerator for Machine Learning Applications

S2RNN: Self-Supervised Reconfigurable Neural Network Hardware Accelerator for Machine Learning Applications

Reconfigurable hardware implementation of K-nearest neighbor algorithm on FPGA

Nowadays, Machine Learning is commonly integrated into most daily life applications in various fields. The K Nearest Neighbor (KNN), which is a robust Machine Learning algorithm, is traditionally used in classification tasks for its simplicity and training-less nature. Hardware accelerators such as FPGAs and ASICs are greatly needed to meet the increased requirements of performance for these applications. It is well known that ASICs are non-programmable and only fabricated once with high expenses, this makes the fabrication of a complete chip for a specific classification problem inefficient. As a better alternative to this challenge, in this work, a reconfigurable hardware architecture of the KNN algorithm is proposed where the employed dataset, the algorithm parameters, and the distance metric used to evaluate the nearest neighbors are all updatable after fabrication, in the ASIC case, or after programming, in the FPGA case. The architecture is also made flexible to accommodate different memory requirements and allow variable arithmetic type and precision selection. Both parameters can be adjusted before fabrication to account only for the expected memory requirement and the fixed point precision required or floating point arithmetic if needed. The proposed architecture is realized on the Genesys 2 board based on Xilinx’s Kintex-7 FPGA. The results obtained from the experiment are consistent with those obtained from the simulation and software analysis. The proposed realization reaches a frequency of up to around 110 MHz and a power consumption of less than 0.4 watts

An In-Depth Analysis of Pythonic Paradigms for Rapid Hardware Prototyping and Instrumentation

This in-depth examination review about pythonic paradigms for quick hardware prototyping and instrumentation to solve the widening gap between the fluidity of software development and the more conventional methodology used in hardware design. The proliferation of specialized hardware and accelerators has resulted in an increased necessity for development strategies that are flexible. Reconfigurable hardware, such as FPGAs and coarse-grain reconfigurable arrays, enables incremental changes in early design stages, which is a key component of agile software development. This article goes into modern agile development methods, emphasizing the integration of services, repositories, and specialized tools to meet particular users' requirements. Continuous improvement in areas such as software and hardware design, testing, analysis, and evaluation, as well as collaboration with current development tools, are all supported by an ecosystem that has been successfully integrated.

Analog Programmable‐Photonic Computation

AbstractDigital electronics is a technological cornerstone in this modern society that has covered the increasing demand for computing power during the last decades thanks to a periodic doubling of transistor density in integrated circuits. Currently, such scaling law is reaching its fundamental limit, leading to the emergence of a large gamut of applications that cannot be supported by digital electronics, specifically, those that involve real‐time multi‐data processing, e.g., medical diagnostic imaging, robotic control, and autonomous driving, among others. In this scenario, an analog computing approach implemented in a real‐time reconfigurable nonelectronic hardware such as programmable integrated photonics (PIP) can be more efficient than digital electronics to perform these emerging applications. However, actual analog computing models such as quantum and neuromorphic computation were not conceived to extract the unique benefits of PIP (and integrated photonics in general). Here, the foundations of a new computation theory are presented, termed Analog Programmable‐Photonic Computation (APC), explicitly designed to unleash the full potential of PIP technology. Interestingly, APC enables overcoming basic theoretical and technological limitations of existing computational models and can be implemented in other technologies (e.g., in electronics, acoustics or using metamaterials), consequently exhibiting the potential to spark a ground‐breaking impact on the information society.

A Deep Learning Network-on-Chip (NoC)-Based Switch-Router to Enhance Information Security in Resource-Constrained Devices

In a resource-constrained environment of the 21st century, the use of hardware-based reconfigurable systems such as Field Programmable Gate Array (FPGAs) is considered an effective way to enhance information security. In comparison with traditional custom circuitry that does not give a flexible approach, it is observed that the reconfigurable hardware shows an excellent potential for cyber security by increasing hardware speeds and flexibility. Therefore, in a quest to integrate multi-core systems, the Network-on-Chip (NoC) has become one of the popular widespread techniques to maximize router security. Due to the significant overhead of chip space and the power consumption of the routers, it is substantially more expensive to construct as compared to a bus-based system. The control component (CC) interacts with the networks that inject packets based on router switching and activity. These control components are coupled with each network to produce a system of controlled networks. The system is further linked with CFM or a Centralized Fabric Manager, which serves as the network’s focal point. After that, the CFM runs the algorithm regularly. The analytic parameters comprise flip flop, power, latency, number of lookup tables (LUTs), and throughput. In the proposed method, the number of LUTs is [Formula: see text], the flip flop is [Formula: see text], the power is [Formula: see text]W, the latency is 5941[Formula: see text]ns, and the planned throughput is 0.56 flits/cycle. Results indicate that the crossbar switch reduces errors and minimizes the delay in the architecture’s outcome level, which further overcomes the descriptions of performance, power throughput, and area delay parameters. The findings of the research can be useful to enhance information security among lightweight devices besides minimizing the chances of network attacks in today’s dynamic and complex cyberspace.

Calibration-Free and Hardware-Efficient Neural Spike Detection for Brain Machine Interfaces.

Recent translational efforts in brain-machine interfaces (BMI) are demonstrating the potential to help people with neurological disorders. The current trend in BMI technology is to increase the number of recording channels to the thousands, resulting in the generation of vast amounts of raw data. This in turn places high bandwidth requirements for data transmission, which increases power consumption and thermal dissipation of implanted systems. On-implant compression and/or feature extraction are therefore becoming essential to limiting this increase in bandwidth, but add further power constraints - the power required for data reduction must remain less than the power saved through bandwidth reduction. Spike detection is a common feature extraction technique used for intracortical BMIs. In this article, we develop a novel firing-rate-based spike detection algorithm that requires no external training and is hardware efficient and therefore ideally suited for real-time applications. Key performance and implementation metrics such as detection accuracy, adaptability in chronic deployment, power consumption, area utilization, and channel scalability are benchmarked against existing methods using various datasets. The algorithm is first validated using a reconfigurable hardware (FPGA) platform and then ported to a digital ASIC implementation in both 65 nm and 0.18 μm CMOS technologies. The 128-channel ASIC design implemented in a 65 nm CMOS technology occupies 0.096 mm2 silicon area and consumes 4.86 μW from a 1.2 V power supply. The adaptive algorithm achieves a 96% spike detection accuracy on a commonly used synthetic dataset, without the need for any prior training.